SLUSE13B January 2020 – November 2021 BQ76952
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
V(ADC_IN_CELLS) | Input voltage range (differential cell input mode)(5) | Internal reference (Vref = VREF1) | –0.2 | 5.5 | V | |
V(ADC_IN) | Input voltage range (ADCIN measurement mode)(6) | Internal reference (Vref = VREF1), applicable to ADCIN measurements using the TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins | –0.2 | VREG18 | V | |
V(ADC_IN_TS) | Input voltage range (external thermistor measurement mode)(7) | Regulator reference (Vref = VREG18), applicable to external thermistor measurements using the TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins | –0.2 | VREG18 | V | |
V(ADC_IN_DIV) | Input voltage range (divider measurement mode)(8) | Internal reference (Vref = VREF1), applicable to divider measurements using the VC16, PACK, and LD pins relative to VSS. | –0.2 | 80 | V | |
B(ADC_INL) | Integral nonlinearity (when using VREF1 and differential cell voltage measurement mode at VC16 - VC15)(4) | 16-bit, best fit over -0.1 V to 5.5 V | –6.6 | 6.6 | LSB(5) | |
16-bit, best fit over -0.2 V to 0.2 V | –4 | 4 | LSB(5) | |||
B(ADC_DNL) | Differential nonlinearity | 16-bit, no missing codes, using differential cell voltage measurement at VC16-VC15 | ±0.12 | LSB(5) | ||
B(ADC_OFF_CELL) | Differential cell offset error | 16-bit, uncalibrated, using VC16 - VC15 | –2.75 | 3.5 | LSB(5) | |
B(ADC_OFF) | ADCIN offset error | 16-bit, uncalibrated, using ADCIN mode on TS1 pin | 0.53 | LSB(6) | ||
B(ADC_OFF_DIV) | Divider offset error | 16-bit, uncalibrated, using divider mode on PACK pin | 0.17 | LSB(8) | ||
B(ADC_OFF_DRIFT_CELL) | Differential cell offset error drift(4) | Offset error measured 16-bit, post calibration, using VC16 - VC15. Drift measured as change in offset over operating temperature range as compared to offset at 30°C. | 0.004 | 0.07 | LSB/°C(5) | |
B(ADC_GAIN) | Gain | Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC16-VC15, uncalibrated. | 5385 | 5406 | 5427 | LSB/V(5) |
B(ADC_GAIN_DRIFT) | Gain drift(4) | Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC16-VC15, uncalibrated. Drift value measured as change in gain over operating temperature range, compared to gain at 30°C. | -0.25 | 0.025 | 0.25 | LSB/V/°C(5) |
R(ADC_IN_CELL) | Effective input resistance(3) | Differential cell input mode on VC16-VC15(9) | 2.1 | MΩ | ||
R(ADC_IN_LD) | Effective input resistance | Divider measurement on LD pin (only active while the LD pin is being measured) | 2 | MΩ | ||
R(ADC_IN_DIV) | Effective input resistance | Divider measurement on VC16 and PACK pins (only active while the pin is being measured) | 600 | kΩ | ||
B(ADC_RES) | Code stability(2) (4) | Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 | 13.5 | 15 | bits | |
B(ADC_RES_FAST) | Code stability in fast mode(2) | Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 | 14 | bits | ||
t(ADC_CONV) | Conversion-time | Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 | 2.93 | ms | ||
t(ADC_CONV_FAST) | Conversion-time in fast mode | Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 | 1.46 | ms |