SLUSFC9 December   2023 BQ76972

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76952
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 REG2 LDO
    14. 6.14 Voltage References
    15. 6.15 Coulomb Counter
    16. 6.16 Coulomb Counter Digital Filter (CC1)
    17. 6.17 Current Measurement Digital Filter (CC2)
    18. 6.18 Current Wake Detector
    19. 6.19 Analog-to-Digital Converter
    20. 6.20 Cell Voltage Measurement Accuracy
    21. 6.21 Cell Balancing
    22. 6.22 Cell Open Wire Detector
    23. 6.23 Internal Temperature Sensor
    24. 6.24 Thermistor Measurement
    25. 6.25 Internal Oscillators
    26. 6.26 High-side NFET Drivers
    27. 6.27 Comparator-Based Protection Subsystem
    28. 6.28 Timing Requirements - I2C Interface, 100kHz Mode
    29. 6.29 Timing Requirements - I2C Interface, 400kHz Mode
    30. 6.30 Timing Requirements - HDQ Interface
    31. 6.31 Timing Requirements - SPI Interface
    32. 6.32 Interface Timing Diagrams
    33. 6.33 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  BQ76972 Device Versions
    4. 7.4  Diagnostics
    5. 7.5  Device Configuration
      1. 7.5.1 Commands and Subcommands
      2. 7.5.2 Configuration Using OTP or Registers
      3. 7.5.3 Device Security
      4. 7.5.4 Scratchpad Memory
    6. 7.6  Measurement Subsystem
      1. 7.6.1  Voltage Measurement
        1. 7.6.1.1 Voltage Measurement Schedule
        2. 7.6.1.2 Usage of VC Pins for Cells Versus Interconnect
        3. 7.6.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.6.2  General Purpose ADCIN Functionality
      3. 7.6.3  Coulomb Counter and Digital Filters
      4. 7.6.4  Synchronized Voltage and Current Measurement
      5. 7.6.5  Internal Temperature Measurement
      6. 7.6.6  Thermistor Temperature Measurement
      7. 7.6.7  Factory Trim of Voltage ADC
      8. 7.6.8  Cell Voltage Measurement Accuracy
        1. 7.6.8.1 Fixed Offset Adjustment
        2. 7.6.8.2 Cell Offset Calibration
      9. 7.6.9  Voltage Calibration (ADC Measurements)
      10. 7.6.10 Voltage Calibration (COV and CUV Protections)
      11. 7.6.11 Current Calibration
      12. 7.6.12 Temperature Calibration
    7. 7.7  Primary and Secondary Protection Subsystems
      1. 7.7.1 Protections Overview
      2. 7.7.2 Primary Protections
      3. 7.7.3 Secondary Protections
      4. 7.7.4 High-Side NFET Drivers
      5. 7.7.5 Protection FETs Configuration and Control
        1. 7.7.5.1 FET Configuration
        2. 7.7.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.7.6 Load Detect Functionality
    8. 7.8  Device Hardware Features
      1. 7.8.1  Voltage References
      2. 7.8.2  ADC Multiplexer
      3. 7.8.3  LDOs
        1. 7.8.3.1 Preregulator Control
        2. 7.8.3.2 REG1 and REG2 LDO Controls
      4. 7.8.4  Standalone Versus Host Interface
      5. 7.8.5  Multifunction Pin Controls
      6. 7.8.6  RST_SHUT Pin Operation
      7. 7.8.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.8.8  ALERT Pin Operation
      9. 7.8.9  DDSG and DCHG Pin Operation
      10. 7.8.10 Fuse Drive
      11. 7.8.11 Cell Open Wire
      12. 7.8.12 Low Frequency Oscillator
      13. 7.8.13 High Frequency Oscillator
    9. 7.9  Device Functional Modes
      1. 7.9.1 Overview
      2. 7.9.2 NORMAL Mode
      3. 7.9.3 SLEEP Mode
      4. 7.9.4 DEEPSLEEP Mode
      5. 7.9.5 SHUTDOWN Mode
      6. 7.9.6 CONFIG_UPDATE Mode
    10. 7.10 Serial Communications Interface
      1. 7.10.1 Serial Communications Overview
      2. 7.10.2 I2C Communications
      3. 7.10.3 SPI Communications
        1. 7.10.3.1 SPI Protocol
      4. 7.10.4 HDQ Communications
    11. 7.11 Cell Balancing
      1. 7.11.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
    7. 8.7 Power Supply Requirements
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.3 Secondary Protections

The BQ76972 device integrates a suite of secondary protection checks on battery operation and status that can trigger a Permanent Fail (PF) if conditions are considered so serious that the pack should be permanently disabled. The various PF checks can be enabled individually based on configuration settings, along with associated thresholds and delays for most checks. When a Permanent Fail has occurred, the BQ76972 device can be configured to either simply provide a flag, to indefinitely disable the protection FETs, or to assert the FUSE pin to permanently disable the pack. The FUSE pin can be used to blow an in-line fuse and also can monitor if a separate secondary protector IC has attempted to blow the fuse.

Because the device stores Permanent Fail status in RAM, that status would be lost when the device resets. To mitigate this, the device can write Permanent Fail status to OTP based on configuration setting. OTP programming may be delayed in low-voltage and high-temperature conditions until OTP programming can reliably be accomplished.

Normally, a Permanent Fail causes the FETs to remain off indefinitely and the fuse may be blown. In that situation, no further action would be taken on further monitoring operations, and charging would no longer be possible. To avoid rapidly draining the battery, the device may be configured to enter DEEPSLEEP mode when a Permanent Fail occurs. Entrance to DEEPSLEEP mode will still be delayed until after fuse blow and OTP programming are completed, if those options are enabled.

When a Permanent Fail occurs, the device may be configured to either turn the REG1 and REG2 LDOs off, or to leave them in their present state. Once disabled, they may still be reenabled through command.

The Permanent Fail checks incorporate a programmable delay to avoid triggering a PF fault on an intermittent condition or measurement. When the threshold is first detected as being met or exceeded by an enabled PF check, the device will set a PF Alert signal, which can be monitored using commands and can also trigger an interrupt on the ALERT pin.

Note: The device only evaluates the conditions for Permanent Fail at one second intervals while in NORMAL and SLEEP modes, it does not continuously compare measurements to the Permanent Fail fault thresholds between intervals. Thus, it is possible for a condition to trigger a PF alert if detected over threshold, but even if the condition drops back below threshold briefly between the one second interval checks, the PF alert would not be cleared until it was detected below threshold at a periodic check.

For more details on the Permanent Fail checks implemented in the BQ76972, refer to the BQ76972 Technical Reference Manual. The secondary protection checks include:

  • Safety Cell Undervoltage Permanent Fail
  • Safety Cell Overvoltage Permanent Fail
  • Safety Overcurrent in Charge Permanent Fail
  • Safety Overcurrent in Discharge Permanent Fail
  • Safety Overtemperature Permanent Fail
  • Safety Overtemperature FET Permanent Fail
  • Copper Deposition Permanent Fail
  • Short Circuit in Discharge Latch Permanent Fail
  • Voltage Imbalance Active Permanent Fail
  • Voltage Imbalance at Rest Permanent Fail
  • Second Level Protector Permanent Fail
  • Discharge FET Permanent Fail
  • Charge FET Permanent Fail
  • OTP Memory Permanent Fail
  • Data ROM Permanent Fail
  • Instruction ROM Permanent Fail
  • Internal LFO Permanent Fail
  • Internal Voltage Reference Permanent Fail
  • Internal VSS Measurement Permanent Fail
  • Internal Stuck Hardware Mux Permanent Fail
  • Commanded Permanent Fail
  • Top of Stack Versus Cell Sum Permanent Fail