SLUSF60 December   2023 BQ77307

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ77307
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Current Detector
    10. 6.10 Thermistor Pullup Resistor
    11. 6.11 Hardware Overtemperature Detector
    12. 6.12 Internal Oscillator
    13. 6.13 Charge and Discharge FET Drivers
    14. 6.14 Protection Subsystem
    15. 6.15 Timing Requirements - I2C Interface, 100kHz Mode
    16. 6.16 Timing Requirements - I2C Interface, 400kHz Mode
    17. 6.17 Timing Diagram
    18. 6.18 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage Protection Subsystem
      2. 7.4.2  Current Protection Subsystem
      3. 7.4.3  Unused VC Pins
      4. 7.4.4  Internal Temperature Protection
      5. 7.4.5  Thermistor Temperature Protections
      6. 7.4.6  Protection FET Drivers
      7. 7.4.7  Voltage References
      8. 7.4.8  Multiplexer
      9. 7.4.9  LDOs
      10. 7.4.10 Standalone Versus Host Interface
      11. 7.4.11 ALERT Pin Operation
      12. 7.4.12 Low Frequency Oscillator
      13. 7.4.13 I2C Serial Communications Interface
    5. 7.5 Protection Subsystem
      1. 7.5.1 Protections Overview
      2. 7.5.2 Primary Protections
      3. 7.5.3 Cell Open Wire Protection
      4. 7.5.4 Diagnostic Checks
    6. 7.6 Device Power Modes
      1. 7.6.1 Overview of Power Modes
      2. 7.6.2 NORMAL Mode
      3. 7.6.3 SHUTDOWN Mode
      4. 7.6.4 CONFIG_UPDATE Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Thermistor Pullup Resistor

Typical values stated where TA = 25°C and VBAT = 25.9 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V to 38.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R(TS_PU) Internal pullup resistance at 25°C(1) 19.75 20 20.25 kΩ
R(TS_PU_DRIFT) Internal pullup resistance change over temperature (1) (2) Change over -20°C/+65°C vs value at 25°C for nominal 20-kΩ –36 28 Ω
R(TS_PU_DRIFT) Internal pullup resistance change over temperature (1) (2) Change over -40°C/+110°C vs value at 25°C for nominal 20-kΩ –53 98 Ω
(1) The internal pullup resistance includes only the resistance between the REG18 internal LDO and the point where the voltage is sensed by the protection subsystem.
(2) Specified by characterization