SLUSC23 September   2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Supply Current
    5. 7.5  Power Supply Control
    6. 7.6  Low-Voltage General Purpose I/O, TS1
    7. 7.7  Power-On Reset (POR)
    8. 7.8  Internal 1.8-V LDO
    9. 7.9  Current Wake Comparator
    10. 7.10 Coulomb Counter
    11. 7.11 ADC Digital Filter
    12. 7.12 ADC Multiplexer
    13. 7.13 Cell Balancing Support
    14. 7.14 Internal Temperature Sensor
    15. 7.15 NTC Thermistor Measurement Support
    16. 7.16 High-Frequency Oscillator
    17. 7.17 Low-Frequency Oscillator
    18. 7.18 Voltage Reference 1
    19. 7.19 Voltage Reference 2
    20. 7.20 Instruction Flash
    21. 7.21 Data Flash
    22. 7.22 Current Protection Thresholds
    23. 7.23 Current Protection Timing
    24. 7.24 N-CH FET Drive (CHG, DSG)
    25. 7.25 I2C and HDQ Interface I/O
    26. 7.26 I2C Interface Timing
    27. 7.27 HDQ Interface Timing
    28. 7.28 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Parameter Measurements
        1. 8.3.1.1 bq78z100 Processor
      2. 8.3.2  Coulomb Counter (CC)
      3. 8.3.3  CC Digital Filter
      4. 8.3.4  ADC Multiplexer
      5. 8.3.5  Analog-to-Digital Converter (ADC)
      6. 8.3.6  ADC Digital Filter
      7. 8.3.7  Internal Temperature Sensor
      8. 8.3.8  External Temperature Sensor Support
      9. 8.3.9  Power Supply Control
      10. 8.3.10 Power-On Reset
      11. 8.3.11 Bus Communication Interface
      12. 8.3.12 Cell Balancing Support
      13. 8.3.13 N-Channel Protection FET Drive
      14. 8.3.14 Low Frequency Oscillator
      15. 8.3.15 High Frequency Oscillator
      16. 8.3.16 1.8-V Low Dropout Regulator
      17. 8.3.17 Internal Voltage References
      18. 8.3.18 Overcurrent in Discharge Protection
      19. 8.3.19 Short-Circuit Current in Charge Protection
      20. 8.3.20 Short-Circuit Current in Discharge 1 and 2 Protection
      21. 8.3.21 Primary Protection Features
      22. 8.3.22 Gas Gauging
      23. 8.3.23 Charge Control Features
      24. 8.3.24 Authentication
    4. 8.4 Device Functional Modes
      1. 8.4.1 Lifetime Logging Features
      2. 8.4.2 Configuration
        1. 8.4.2.1 Coulomb Counting
        2. 8.4.2.2 Cell Voltage Measurements
        3. 8.4.2.3 Current Measurements
        4. 8.4.2.4 Auto Calibration
        5. 8.4.2.5 Temperature Measurements
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements (Default)
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Design Parameters
      3. 9.2.3 Calibration Process
      4. 9.2.4 Gauging Data Updates
        1. 9.2.4.1 Application Curve
  10. 10Power Supply Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

bq78z100 Pinout.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DRZ
VSS 1 P Device ground
SRN 2 IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor.
SRP 3 IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor.
TS1 4 IA Input for ADC to the oversampled ADC channel
SCL 5 I/O Serial Clock for the I2C interface; requires an external pullup when used
SDA/HDQ 6 I/O Serial Data for the I2C and HDQ interfaces; requires an external pullup
DSG 7 O N-Channel FET drive output pin
PACK 8 IA, P Pack sense input pin
CHG 9 O N-Channel FET drive output pin
PBI 10 P Power supply backup input pin
VC2 11 IA, P Sense voltage input pin for most positive cell, balance current input for most positive cell. Primary power supply input and battery stack measurement input (BAT)
VC1 12 IA Sense voltage input pin for least positive cell, balance current input for least positive cell
PWPD — Exposed Pad, electrically connected to VSS (external trace)