SLUSF21 june   2023 BQ79616

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
        1. 8.3.1.1 AVAO_REF and AVDD_REF
        2. 8.3.1.2 LDOIN
        3. 8.3.1.3 AVDD
        4. 8.3.1.4 DVDD
        5. 8.3.1.5 CVDD and NEG5V
        6. 8.3.1.6 TSREF
      2. 8.3.2 Measurement System
        1. 8.3.2.1 Main ADC
          1. 8.3.2.1.1 Cell Voltage Measurements
            1. 8.3.2.1.1.1 Analog Front End
            2. 8.3.2.1.1.2 VC Channel Measurements
            3. 8.3.2.1.1.3 Post-ADC Digital LPF
            4. 8.3.2.1.1.4 BBP and BBN Measurements
          2. 8.3.2.1.2 Temperature Measurements
            1. 8.3.2.1.2.1 DieTemp1 Measurement
            2. 8.3.2.1.2.2 GPIOs and TSREF Measurements
          3. 8.3.2.1.3 Main ADC Operation Control
            1. 8.3.2.1.3.1 Operation Modes and Status
        2. 8.3.2.2 AUX ADC
          1. 8.3.2.2.1 AUX Cell Voltage Measurements
            1. 8.3.2.2.1.1 AUX Analog Front End
            2. 8.3.2.2.1.2 CB and BB Channel Measurements
          2. 8.3.2.2.2 AUX Temperature Measurements
            1. 8.3.2.2.2.1 DieTemp2 Measurement
            2. 8.3.2.2.2.2 AUX GPIO Measurements
          3. 8.3.2.2.3 MISC Measurements
          4. 8.3.2.2.4 AUX ADC Operation Control
        3. 8.3.2.3 Synchronization Between MAIN and AUX ADC Measurements
      3. 8.3.3 Cell Balancing
        1. 8.3.3.1 Set Up Cell Balancing
          1. 8.3.3.1.1 Step 1: Determine Balancing Channels
          2. 8.3.3.1.2 Step 2: Select Balancing Control Methods
          3. 8.3.3.1.3 Step 3a: Balancing Thermal Management
          4. 8.3.3.1.4 Step 3b: Option to Stop On Cell Voltage Threshold
          5. 8.3.3.1.5 Step 3c: Option to Stop at Fault
        2. 8.3.3.2 Cell Balancing in SLEEP Mode
        3. 8.3.3.3 Pause and Stop Cell Balancing
          1. 8.3.3.3.1 Cell Balancing Pause
          2. 8.3.3.3.2 Cell Balancing Stop
          3. 8.3.3.3.3 Remaining CB Time
        4. 8.3.3.4 Module Balancing
          1. 8.3.3.4.1 Start Module Balancing
          2. 8.3.3.4.2 Stop Module Balancing
      4. 8.3.4 Integrated Hardware Protectors
        1. 8.3.4.1 OVUV Protectors
          1. 8.3.4.1.1 OVUV Operation Modes
          2. 8.3.4.1.2 OVUV Control and Status
            1. 8.3.4.1.2.1 OVUV Control
            2. 8.3.4.1.2.2 OVUV Status
        2. 8.3.4.2 OTUT Protector
          1. 8.3.4.2.1 OTUT Operation Modes
          2. 8.3.4.2.2 OTUT Control and Status
            1. 8.3.4.2.2.1 OTUT Control
            2. 8.3.4.2.2.2 OTUT Status
      5. 8.3.5 GPIO Configuration
      6. 8.3.6 Communication, OTP, Diagnostic Control
        1. 8.3.6.1 Communication
          1. 8.3.6.1.1 Serial Interface
            1. 8.3.6.1.1.1 UART Physical Layer
              1. 8.3.6.1.1.1.1 UART Transmitter
              2. 8.3.6.1.1.1.2 UART Receiver
              3. 8.3.6.1.1.1.3 COMM CLEAR
            2. 8.3.6.1.1.2 Command and Response Protocol
              1. 8.3.6.1.1.2.1 Transaction Frame Structure
                1. 8.3.6.1.1.2.1.1 Frame Initialization Byte
                2. 8.3.6.1.1.2.1.2 Device Address Byte
                3. 8.3.6.1.1.2.1.3 Register Address Bytes
                4. 8.3.6.1.1.2.1.4 Data Bytes
                5. 8.3.6.1.1.2.1.5 CRC Bytes
                6. 8.3.6.1.1.2.1.6 Calculating Frame CRC Value
                7. 8.3.6.1.1.2.1.7 Verifying Frame CRC
              2. 8.3.6.1.1.2.2 Transaction Frame Examples
                1. 8.3.6.1.1.2.2.1 Single Device Read/Write
                2. 8.3.6.1.1.2.2.2 Stack Read/Write
                3. 8.3.6.1.1.2.2.3 Broadcast Read/Write
                4. 8.3.6.1.1.2.2.4 Broadcast Write Reverse Direction
          2. 8.3.6.1.2 Daisy Chain Interface
            1. 8.3.6.1.2.1 Daisy Chain Transmitter and Receiver Functionality
            2. 8.3.6.1.2.2 Daisy Chain Protocol
          3. 8.3.6.1.3 Start Communication
            1. 8.3.6.1.3.1 Identify Base and Stack
            2. 8.3.6.1.3.2 Auto-Addressing
              1. 8.3.6.1.3.2.1 Setting Up the Device Addresses
              2. 8.3.6.1.3.2.2 Setting Up COMM_CTRL[STACK_DEV] and [TOP_STACK]
              3. 8.3.6.1.3.2.3 Storing Device Address to OTP
            3. 8.3.6.1.3.3 Synchronize Daisy Chain DLL
            4. 8.3.6.1.3.4 Ring Communication
          4. 8.3.6.1.4 Communication Timeout
            1. 8.3.6.1.4.1 Short Communication Timeout
            2. 8.3.6.1.4.2 Long Communication Timeout
          5. 8.3.6.1.5 Communication Debug Mode
          6. 8.3.6.1.6 Multidrop Configuration
          7. 8.3.6.1.7 SPI Controller
          8. 8.3.6.1.8 SPI Loopback
        2. 8.3.6.2 Fault Handling
          1. 8.3.6.2.1 Fault Status Hierarchy
            1. 8.3.6.2.1.1 Debug Registers
          2. 8.3.6.2.2 Fault Masking and Reset
            1. 8.3.6.2.2.1 Fault Masking
            2. 8.3.6.2.2.2 Fault Reset
          3. 8.3.6.2.3 Fault Signaling
            1. 8.3.6.2.3.1 Fault Status Transmitting in ACTIVE Mode
            2. 8.3.6.2.3.2 Fault Status Transmitting in SLEEP Mode
            3. 8.3.6.2.3.3 Heartbeat and Fault Tone
        3. 8.3.6.3 Nonvolatile Memory
          1. 8.3.6.3.1 OTP Page Status
          2. 8.3.6.3.2 OTP Programming
        4. 8.3.6.4 Diagnostic Control/Status
          1. 8.3.6.4.1 Power Supplies Check
            1. 8.3.6.4.1.1 Power Supply Diagnostic Check
            2. 8.3.6.4.1.2 Power Supply BIST
          2. 8.3.6.4.2 Thermal Shutdown and Warning Check
            1. 8.3.6.4.2.1 Thermal Shutdown
            2. 8.3.6.4.2.2 Thermal Warning
          3. 8.3.6.4.3 Oscillators Watchdog
          4. 8.3.6.4.4 OTP Error Check
            1. 8.3.6.4.4.1 OTP CRC Test and Faults
            2. 8.3.6.4.4.2 OTP Margin Read
            3. 8.3.6.4.4.3 Error Check and Correct (ECC) OTP
          5. 8.3.6.4.5 Integrated Hardware Protector Check
            1. 8.3.6.4.5.1 Parity Check
            2. 8.3.6.4.5.2 OVUV and OTUT DAC Check
            3. 8.3.6.4.5.3 OVUV Protector BIST
            4. 8.3.6.4.5.4 OTUT Protector BIST
          6. 8.3.6.4.6 Diagnostic Through ADC Comparison
            1. 8.3.6.4.6.1 Cell Voltage Measurement Check
            2. 8.3.6.4.6.2 Temperature Measurement Check
            3. 8.3.6.4.6.3 Cell Balancing FETs Check
            4. 8.3.6.4.6.4 VC and CB Open Wire Check
      7. 8.3.7 Bus Bar Support
        1. 8.3.7.1 Bus Bar on BBP/BBN Pins
          1. 8.3.7.1.1 Typical Connection
          2. 8.3.7.1.2 Bus Bar Measurement
          3. 8.3.7.1.3 Cell Balancing Handling
          4. 8.3.7.1.4 Cell Voltage Diagnostic Control
        2. 8.3.7.2 Bus Bar on Individual VC Channel
          1. 8.3.7.2.1 Typical Connection
          2. 8.3.7.2.2 Bus Bar Measurement
          3. 8.3.7.2.3 Cell Balancing Handling
          4. 8.3.7.2.4 Cell Voltage Diagnostic Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 SHUTDOWN Mode
          1. 8.4.1.1.1 Exit SHUTDOWN Mode
          2. 8.4.1.1.2 Enter SHUTDOWN Mode
        2. 8.4.1.2 SLEEP Mode
          1. 8.4.1.2.1 Exit SLEEP Mode
          2. 8.4.1.2.2 Enter SLEEP Mode
        3. 8.4.1.3 ACTIVE Mode
          1. 8.4.1.3.1 Exit ACTIVE Mode
          2. 8.4.1.3.2 Enter ACTIVE Mode from SHUTDOWN Mode
          3. 8.4.1.3.3 Enter ACTIVE Mode from SLEEP Mode
      2. 8.4.2 Device Reset
      3. 8.4.3 Ping and Tone
        1. 8.4.3.1 Ping
        2. 8.4.3.2 Tone
        3. 8.4.3.3 Ping and Tone Propagation
    5. 8.5 Register Maps
      1. 8.5.1 OTP Shadow Register Summary
      2. 8.5.2 Read/Write Register Summary
      3. 8.5.3 Read-Only Register Summary
      4. 8.5.4 Register Field Descriptions
        1. 8.5.4.1  Device Addressing Setup
          1. 8.5.4.1.1 DIR0_ADDR_OTP
          2. 8.5.4.1.2 DIR1_ADDR_OTP
          3. 8.5.4.1.3 CUST_MISC1 through CUST_MISC8
          4. 8.5.4.1.4 DIR0_ADDR
          5. 8.5.4.1.5 DIR1_ADDR
        2. 8.5.4.2  Device ID and Scratch Pad
          1. 8.5.4.2.1 PARTID
          2. 8.5.4.2.2 DEV_REVID
          3. 8.5.4.2.3 DIE_ID1 through DIE_ID9
        3. 8.5.4.3  General Configuration and Control
          1. 8.5.4.3.1  DEV_CONF
          2. 8.5.4.3.2  ACTIVE_CELL
          3. 8.5.4.3.3  BBVC_POSN1
          4. 8.5.4.3.4  BBVC_POSN2
          5. 8.5.4.3.5  PWR_TRANSIT_CONF
          6. 8.5.4.3.6  COMM_TIMEOUT_CONF
          7. 8.5.4.3.7  TX_HOLD_OFF
          8. 8.5.4.3.8  STACK_RESPONSE
          9. 8.5.4.3.9  BBP_LOC
          10. 8.5.4.3.10 COMM_CTRL
          11. 8.5.4.3.11 CONTROL1
          12. 8.5.4.3.12 CONTROL2
          13. 8.5.4.3.13 CUST_CRC_HI
          14. 8.5.4.3.14 CUST_CRC_LO
          15. 8.5.4.3.15 CUST_CRC_RSLT_HI
          16. 8.5.4.3.16 CUST_CRC_RSLT_LO
        4. 8.5.4.4  Operation Status
          1. 8.5.4.4.1 DIAG_STAT
          2. 8.5.4.4.2 ADC_STAT1
          3. 8.5.4.4.3 ADC_STAT2
          4. 8.5.4.4.4 GPIO_STAT
          5. 8.5.4.4.5 BAL_STAT
          6. 8.5.4.4.6 DEV_STAT
        5. 8.5.4.5  ADC Configuration and Control
          1. 8.5.4.5.1 ADC_CONF1
          2. 8.5.4.5.2 ADC_CONF2
          3. 8.5.4.5.3 MAIN_ADC_CAL1
          4. 8.5.4.5.4 MAIN_ADC_CAL2
          5. 8.5.4.5.5 AUX_ADC_CAL1
          6. 8.5.4.5.6 AUX_ADC_CAL2
          7. 8.5.4.5.7 ADC_CTRL1
          8. 8.5.4.5.8 ADC_CTRL2
          9. 8.5.4.5.9 ADC_CTRL3
        6. 8.5.4.6  ADC Measurement Results
          1. 8.5.4.6.1  VCELL16_HI/LO
          2. 8.5.4.6.2  VCELL15_HI/LO
          3. 8.5.4.6.3  VCELL14_HI/LO
          4. 8.5.4.6.4  VCELL13_HI/LO
          5. 8.5.4.6.5  VCELL12_HI/LO
          6. 8.5.4.6.6  VCELL11_HI/LO
          7. 8.5.4.6.7  VCELL10_HI/LO
          8. 8.5.4.6.8  VCELL9_HI/LO
          9. 8.5.4.6.9  VCELL8_HI/LO
          10. 8.5.4.6.10 VCELL7_HI/LO
          11. 8.5.4.6.11 VCELL6_HI/LO
          12. 8.5.4.6.12 VCELL5_HI/LO
          13. 8.5.4.6.13 VCELL4_HI/LO
          14. 8.5.4.6.14 VCELL3_HI/LO
          15. 8.5.4.6.15 VCELL2_HI/LO
          16. 8.5.4.6.16 VCELL1_HI/LO
          17. 8.5.4.6.17 BUSBAR_HI/LO
          18. 8.5.4.6.18 TSREF_HI/LO
          19. 8.5.4.6.19 GPIO1_HI/LO
          20. 8.5.4.6.20 GPIO2_HI/LO
          21. 8.5.4.6.21 GPIO3_HI/LO
          22. 8.5.4.6.22 GPIO4_HI/LO
          23. 8.5.4.6.23 GPIO5_HI/LO
          24. 8.5.4.6.24 GPIO6_HI/LO
          25. 8.5.4.6.25 GPIO7_HI/LO
          26. 8.5.4.6.26 GPIO8_HI/LO
          27. 8.5.4.6.27 DIETEMP1_HI/LO
          28. 8.5.4.6.28 DIETEMP2_HI/LO
          29. 8.5.4.6.29 AUX_CELL_HI/LO
          30. 8.5.4.6.30 AUX_GPIO_HI/LO
          31. 8.5.4.6.31 AUX_BAT_HI/LO
          32. 8.5.4.6.32 AUX_REFL_HI/LO
          33. 8.5.4.6.33 AUX_VBG2_HI/LO
          34. 8.5.4.6.34 AUX_AVAO_REF_HI/LO
          35. 8.5.4.6.35 AUX_AVDD_REF_HI/LO
          36. 8.5.4.6.36 AUX_OV_DAC_HI/LO
          37. 8.5.4.6.37 AUX_UV_DAC_HI/LO
          38. 8.5.4.6.38 AUX_OT_OTCB_DAC_HI/LO
          39. 8.5.4.6.39 AUX_UT_DAC_HI/LO
          40. 8.5.4.6.40 AUX_VCBDONE_DAC_HI/LO
          41. 8.5.4.6.41 AUX_VCM_HI/LO
          42. 8.5.4.6.42 REFOVDAC_HI/LO
          43. 8.5.4.6.43 DIAG_MAIN_HI/LO
          44. 8.5.4.6.44 DIAG_AUX_HI/LO
        7. 8.5.4.7  Balancing Configuration, Control and Status
          1. 8.5.4.7.1  CB_CELL16_CTRL through CB_CELL1_CTRL
          2. 8.5.4.7.2  VMB_DONE_THRESH
          3. 8.5.4.7.3  MB_TIMER_CTRL
          4. 8.5.4.7.4  VCB_DONE_THRESH
          5. 8.5.4.7.5  OTCB_THRESH
          6. 8.5.4.7.6  BAL_CTRL1
          7. 8.5.4.7.7  BAL_CTRL2
          8. 8.5.4.7.8  BAL_CTRL3
          9. 8.5.4.7.9  CB_COMPLETE1
          10. 8.5.4.7.10 CB_COMPLETE2
          11. 8.5.4.7.11 BAL_TIME
        8. 8.5.4.8  Protector Configuration and Control
          1. 8.5.4.8.1 OV_THRESH
          2. 8.5.4.8.2 UV_THRESH
          3. 8.5.4.8.3 UV_DISABLE1
          4. 8.5.4.8.4 UV_DISABLE2
          5. 8.5.4.8.5 OTUT_THRESH
          6. 8.5.4.8.6 OVUV_CTRL
          7. 8.5.4.8.7 OTUT_CTRL
        9. 8.5.4.9  GPIO Configuration
          1. 8.5.4.9.1 GPIO_CONF1
          2. 8.5.4.9.2 GPIO_CONF2
          3. 8.5.4.9.3 GPIO_CONF3
          4. 8.5.4.9.4 GPIO_CONF4
        10. 8.5.4.10 SPI Controller
          1. 8.5.4.10.1 SPI_CONF
          2. 8.5.4.10.2 SPI_EXE
          3. 8.5.4.10.3 SPI_TX3, SPI_TX2, and SPI_TX1
          4. 8.5.4.10.4 SPI_RX3, SPI_RX2, and SPI_RX1
        11. 8.5.4.11 Diagnostic Control
          1. 8.5.4.11.1  DIAG_OTP_CTRL
          2. 8.5.4.11.2  DIAG_COMM_CTRL
          3. 8.5.4.11.3  DIAG_PWR_CTRL
          4. 8.5.4.11.4  DIAG_CBFET_CTRL1
          5. 8.5.4.11.5  DIAG_CBFET_CTRL2
          6. 8.5.4.11.6  DIAG_COMP_CTRL1
          7. 8.5.4.11.7  DIAG_COMP_CTRL2
          8. 8.5.4.11.8  DIAG_COMP_CTRL3
          9. 8.5.4.11.9  DIAG_COMP_CTRL4
          10. 8.5.4.11.10 DIAG_PROT_CTRL
        12. 8.5.4.12 Fault Configuration and Reset
          1. 8.5.4.12.1 FAULT_MSK1
          2. 8.5.4.12.2 FAULT_MSK2
          3. 8.5.4.12.3 FAULT_RST1
          4. 8.5.4.12.4 FAULT_RST2
        13. 8.5.4.13 Fault Status
          1. 8.5.4.13.1  FAULT_SUMMARY
          2. 8.5.4.13.2  FAULT_COMM1
          3. 8.5.4.13.3  FAULT_COMM2
          4. 8.5.4.13.4  FAULT_COMM3
          5. 8.5.4.13.5  FAULT_OTP
          6. 8.5.4.13.6  FAULT_SYS
          7. 8.5.4.13.7  FAULT_PROT1
          8. 8.5.4.13.8  FAULT_PROT2
          9. 8.5.4.13.9  FAULT_OV1
          10. 8.5.4.13.10 FAULT_OV2
          11. 8.5.4.13.11 FAULT_UV1
          12. 8.5.4.13.12 FAULT_UV2
          13. 8.5.4.13.13 FAULT_OT
          14. 8.5.4.13.14 FAULT_UT
          15. 8.5.4.13.15 FAULT_COMP_GPIO
          16. 8.5.4.13.16 FAULT_COMP_VCCB1
          17. 8.5.4.13.17 FAULT_COMP_VCCB2
          18. 8.5.4.13.18 FAULT_COMP_VCOW1
          19. 8.5.4.13.19 FAULT_COMP_VCOW2
          20. 8.5.4.13.20 FAULT_COMP_CBOW1
          21. 8.5.4.13.21 FAULT_COMP_CBOW2
          22. 8.5.4.13.22 FAULT_COMP_CBFET1
          23. 8.5.4.13.23 FAULT_COMP_CBFET2
          24. 8.5.4.13.24 FAULT_COMP_MISC
          25. 8.5.4.13.25 FAULT_PWR1
          26. 8.5.4.13.26 FAULT_PWR2
          27. 8.5.4.13.27 FAULT_PWR3
        14. 8.5.4.14 Debug Control and Status
          1. 8.5.4.14.1  DEBUG_CTRL_UNLOCK
          2. 8.5.4.14.2  DEBUG_COMM_CTRL1
          3. 8.5.4.14.3  DEBUG_COMM_CTRL2
          4. 8.5.4.14.4  DEBUG_COMM_STAT
          5. 8.5.4.14.5  DEBUG_UART_RC
          6. 8.5.4.14.6  DEBUG_UART_RR_TR
          7. 8.5.4.14.7  DEBUG_COMH_BIT
          8. 8.5.4.14.8  DEBUG_COMH_RC
          9. 8.5.4.14.9  DEBUG_COMH_RR_TR
          10. 8.5.4.14.10 DEBUG_COML_BIT
          11. 8.5.4.14.11 DEBUG_COML_RC
          12. 8.5.4.14.12 DEBUG_COML_RR_TR
          13. 8.5.4.14.13 DEBUG_UART_DISCARD
          14. 8.5.4.14.14 DEBUG_COMH_DISCARD
          15. 8.5.4.14.15 DEBUG_COML_DISCARD
          16. 8.5.4.14.16 DEBUG_UART_VALID_HI/LO
          17. 8.5.4.14.17 DEBUG_COMH_VALID_HI/LO
          18. 8.5.4.14.18 DEBUG_COML_VALID_HI/LO
          19. 8.5.4.14.19 DEBUG_OTP_SEC_BLK
          20. 8.5.4.14.20 DEBUG_OTP_DED_BLK
        15. 8.5.4.15 OTP Programming Control and Status
          1. 8.5.4.15.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
          2. 8.5.4.15.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
          3. 8.5.4.15.3 OTP_PROG_CTRL
          4. 8.5.4.15.4 OTP_ECC_TEST
          5. 8.5.4.15.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
          6. 8.5.4.15.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
          7. 8.5.4.15.7 OTP_PROG_STAT
          8. 8.5.4.15.8 OTP_CUST1_STAT
          9. 8.5.4.15.9 OTP_CUST2_STAT
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Base Device Application Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Cell Sensing and Balancing Inputs
          2. 9.2.1.2.2 BAT and External NPN
          3. 9.2.1.2.3 Power Supplies, Reference Input
          4. 9.2.1.2.4 GPIO For Thermistor Inputs
          5. 9.2.1.2.5 Internal Balancing Current
          6. 9.2.1.2.6 UART, NFAULT
          7. 9.2.1.2.7 Daisy Chain Isolation
            1. 9.2.1.2.7.1 Devices Connected on the Same PCB
            2. 9.2.1.2.7.2 Devices Connected on Different PCBs
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Daisy Device Application Circuit
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Bypass Capacitors for Power Supplies and Reference
      3. 11.1.3 Cell Voltage Sensing
      4. 11.1.4 Daisy Chain Communication
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
POWER STATE TIMING
tSU(WAKE_SHUT)Startup from SHUTDOWN to ACTIVE modeBase device: From the end of WAKE ping to the start of a forwarding WAKE tone610ms
Stack device: From the end of a received WAKE tone to the start of a forwarding WAKE tone610ms
tSU(SLP2ACT)Startup from SLEEP to ACTIVE mode (with SLEEP2ACTIVE ping/tone)Base device: From the end of  SLEEP2ACTIVE ping to the start of the forwarding SLEEP2ACTIVE tone230µs
Stack device: From the end of  SLEEP2ACTIVE tone to the start of the forwarding SLEEP2ACTIVE tone230µs
tSU(WAKE_SLP)Startup from SLEEP to ACTIVE mode (with WAKE ping/tone)Base device: From the end of WAKE ping to the start of a forwarding WAKE tone1ms
Stack device: From the end of a received WAKE tone to the start of a forwarding WAKE tone1ms
tSLPFrom ACTIVE to SLEEP modeFrom receiving SLEEP entry condition to enter in SLEEP mode100µs
tSHTDNFrom ACTIVE to SLHUTDOWN modeFrom receiving SHUTDOWN entry condition to enter in SHUTDOWN mode (all LDOs in 10% of their nominal value)20ms
tRSTReset time during ACTIVE modeCONTROL1[SOFT_RST] = 1 is sent to a completion of the digital reset1ms
tHWRSTThe time device will be in HW reset, after HW reset ping/tone issued 75ms
SUPPLIES TIMING
tTSREF_ONTSREF ramp up time (10%–90%)CTSREF = 1 µF6ms
tTSREF_OFFTSREF ramp down time (90%–10%)CTSREF = 1 µF8ms
PING SIGNAL TIMING
tHLD_WAKEWAKE ping low time on RX pin; no external load on CVDD22.5ms
tHLD_SDSHUTDOWN ping low time on RX pin; no external load on CVDD710ms
tUART(StA)SLEEPtoACTIVE ping low time on RX pin250300µs
tHLD_HWRSTHW_RESET ping low time on RX pin36ms
COML and COMH (PULSE and TONE TIMING)
tPW_DCCOMM: Pulse width of data (half bit time) for communication 250ns
tRECLK_DCCOMM: data reclocking delay per device from COMH to COML or vice versa 45µs
tCOMTONETime between pulses of comm tones (HFO based). Comm Tones are WAKE, SLEEPtoACTIVE, SHUTDOWN, HWRST tones1115µs
tCOMMTONE_HIThe HIGH time of each comms pulse (HFO base)0.9211.08µs
tCOMMTONE_LOThe LOW time of each comms pulse (HFO base)0.9211.08µs
tFLTTONETime between pulses of FAULT Tone (LFO based). Applies to FAULT Tone and HEARTBEAT11.5µs
tFLTTONE_HIThe HIGH time of each pulse of the tone couplet1µs
tFLTTONE_LOThe LOW time of each pulse of the tone couplet1µs
nWAKEDETNumber of pulses to detect as a WAKE tone60pulses
nWAKENumber of pulses to transit for a WAKE tone90pulses
nSHDNDETNumber of pulses to detect as a SHUTDOWN tone180pulses
nSHDNNumber of pulses to transit for a SHUTDOWN tone270pulses
nSLPtoACTDETNumber of pulses to detect as a SLEEPtoACTIVE tone20pulses
nSLPtoACTNumber of pulses to transit for a SLEEPtoACTIVE tone30pulses
nHWRSTDETNumber of pulses to detect as a HW_RESET tone540pulses
nHWRSTNumber of pulses to transit for a HW_RESET tone810pulses
nHBDETHEARTBEAT: Number of pulses to detect as a valid tone 20 pulses
nHBHEARTBEAT: Number of pulses to transit for a tone 30 pulses
tHB_PERIODHEARTBEAT: Period between HEARTBEAT  burst (from the beginning of a HEARTBEAT to the beginning of the next HEARTBEAT)360400440ms
tHB_TIMEOUTHEARTBEAT: Timeout to considered as not receiving HEARTBEAT 0.911.1s
tHB_FASTHEARTBEAT: If HEARTBEAT is received within this time, it is considered receiving HEARTBEAT too fast  200 ms
nFTONEDETFAULT TONE: Number of pulses  to detect as a valid tone 60 pulses
nFTONEFAULT TONE: Number of pulses to transit for a tone 90 pulses
tFTONE_PERIODFAULT TONE: Period between FAULT TONE Burst (from the beginning of a FAULT TONE to the beginning of the next
FAULT TONE)		 50 ms
tFTS_LATENCYFault tone latency in stack deviceFrom time a device receive the tone to the time the same device detects and generate its fault tone48µs
tFTB_LATENCYFault tone latency in base deviceFrom the time a device receive the tone to the time the same device detects and asserts NFAULT24µs
MAIN and AUX ADC TIMING
tSAR_CONVSingle conversion time (both Main and AUX ADCs)  8 µs
tMAIN_ADC_CYCLESingle round robin cycle (Main ADC) 192 µs
tAUX_ADC_CYCLESingle round robin cycle (AUX ADC) 192 µs
tAFE_SETTLEAnalog front end (level shifters) settling time whenever device enter ACTIVE mode from SLEEP or SHUTDOWN 4 ms
tADC_ACCThis includes mux round robin, ADC conversions, and digital filters.-1.51.5%
BALANCING TIMING
tBAL_ACCBalancing timer accuracy-55%
HW COMPARATORS/PROTECTORS TIMING
tOV_CYCLEOV round robin cycle 8 ms
tUV_CYCLEUV round robin cycle 8 ms
tOVUV_BIST_CYCLEOV and UV BIST cycle21.82324.2ms
tOT_CYCLEOT round robin cycle 4ms
tUT_CYCLEUT round robin cycle 4 ms
tPWR_BIST_CYCLETime needed for the power supply BIST to complete after the power BIST go command10.911.512.1ms
tOTUT_BIST_CYCLEOT and UT BIST cycle192021ms
tHW_COMP_ACCOV,UV,OT,UT comparators timing accuracy-55%
I/O TIMING (TX, RX, GPIO, NFAULT)
tRISERise TimeVCVDD  > MIN VCVDD, CLOAD = 150 pF, GPIO in output mode 12ns
tFALLFall Time (exclude NFAULT)VCVDD  > MIN VCVDD, CLOAD = 150 pF, GPIO in output mode 7ns
tFALL_NFAULTFall Time on NFAULTVCVDD  > MIN VCVDD, CLOAD = 150 pF, RPULLUP = 10 kΩ 100ns
UART TIMING
UARTBAUDUART TX/RX Baud Rate1Mbps
UARTERR_BAUD(RX)UART RX baud rate error - requirement on the external host-1 1%
UARTERR_BAUD(TX)UART TX baud rate error-1.5 1.5%
tUART(CLR)UART Clear low time15 20bit period
tUART(RX_HIGH)After COMM CLEAR, wait this time before sending new frame1  bit period
OTP NVM TIMING
tCRC_CUSTTime to complete a single cycle of CRC check on the customer OTP space175µs
tCRC_FACTTime to complete a single cycle of CRC check on the factory OTP space1.6ms
SPI CONTROLLER TIMING
fSCLKSCLK frequency 450500550kHz
tHIGH, tLOW SCLK duty cycle 50%
tSS(HIGH)SS HIGH latency time. Time from register write high to SS pin high  4 µs
tSS(LOW)SS LOW latency time. Time from register write low to SS pin low  4 µs
tSU(MISO)MISO input data setup time-requirement for target deviceMISO stable before SCLK transition100  ns
tHD(MISO)MISO input data hold timeMISO stable after SCLK transition 0 ns
OSCILLATOR
fHFOHigh frequency oscillator31.523232.48MHz
fLFOLow frequency oscillator248.9262275.1kHz