SLUSEC2A December   2021  – November 2023 BQ79631-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Measurement System
        1. 8.3.1.1 Voltage Measurement System
          1. 8.3.1.1.1 Main ADC
            1. 8.3.1.1.1.1 VS Voltage Measurements
              1. 8.3.1.1.1.1.1 Analog Front End
              2. 8.3.1.1.1.1.2 VS Channel Measurements
              3. 8.3.1.1.1.1.3 Post-ADC Digital LPF
              4. 8.3.1.1.1.1.4 SRP and SRN Measurements
            2. 8.3.1.1.1.2 Temperature Measurements
              1. 8.3.1.1.1.2.1 DieTemp1 Measurement
              2. 8.3.1.1.1.2.2 GPIOs and TSREF Measurements
            3. 8.3.1.1.1.3 Main ADC Operation Control
              1. 8.3.1.1.1.3.1 Operation Modes and Status
          2. 8.3.1.1.2 AUX ADC
            1. 8.3.1.1.2.1 AUX Voltage Measurements
              1. 8.3.1.1.2.1.1 AUX Analog Front End
              2. 8.3.1.1.2.1.2 AUX Channel Measurements
            2. 8.3.1.1.2.2 AUX Temperature Measurements
              1. 8.3.1.1.2.2.1 DieTemp2 Measurement
              2. 8.3.1.1.2.2.2 AUX GPIO Measurements
            3. 8.3.1.1.2.3 MISC Measurements
            4. 8.3.1.1.2.4 AUX ADC Operation Control
          3. 8.3.1.1.3 Synchronization Between MAIN and AUX ADC Measurements
        2. 8.3.1.2 Current Sense ADC
      2. 8.3.2 OVUV Detection
        1. 8.3.2.1 OVUV Operation Modes
        2. 8.3.2.2 OVUV Control and Status
          1. 8.3.2.2.1 OVUV Control
          2. 8.3.2.2.2 OVUV Status
      3. 8.3.3 Power Supplies
        1. 8.3.3.1 AVAO_REF and AVDD_REF
        2. 8.3.3.2 LDOIN
        3. 8.3.3.3 AVDD
        4. 8.3.3.4 DVDD
        5. 8.3.3.5 CVDD and NEG5V
        6. 8.3.3.6 TSREF
      4. 8.3.4 GPIO Configuration
      5. 8.3.5 Communication, OTP, Diagnostic Control
        1. 8.3.5.1 Communication
          1. 8.3.5.1.1 Serial Interface
            1. 8.3.5.1.1.1 UART Physical Layer
              1. 8.3.5.1.1.1.1 UART Transmitter
              2. 8.3.5.1.1.1.2 UART Receiver
              3. 8.3.5.1.1.1.3 COMM CLEAR
            2. 8.3.5.1.1.2 Command and Response Protocol
              1. 8.3.5.1.1.2.1 Transaction Frame Structure
                1. 8.3.5.1.1.2.1.1 Frame Initialization Byte
                2. 8.3.5.1.1.2.1.2 Device Address Byte
                3. 8.3.5.1.1.2.1.3 Register Address Bytes
                4. 8.3.5.1.1.2.1.4 Data Bytes
                5. 8.3.5.1.1.2.1.5 CRC Bytes
                6. 8.3.5.1.1.2.1.6 Calculating Frame CRC Value
                7. 8.3.5.1.1.2.1.7 Verifying Frame CRC
              2. 8.3.5.1.1.2.2 Transaction Frame Examples
                1. 8.3.5.1.1.2.2.1 Single Device Read/Write
                2. 8.3.5.1.1.2.2.2 Stack Read/Write
                3. 8.3.5.1.1.2.2.3 Broadcast Read/Write
                4. 8.3.5.1.1.2.2.4 Broadcast Write Reverse Direction
          2. 8.3.5.1.2 Daisy-Chain Interface
            1. 8.3.5.1.2.1 Daisy-Chain Transmitter and Receiver Functionality
            2. 8.3.5.1.2.2 Daisy-Chain Protocol
          3. 8.3.5.1.3 Start Communication
            1. 8.3.5.1.3.1 Identify Base and Stack
            2. 8.3.5.1.3.2 Auto-Addressing
              1. 8.3.5.1.3.2.1 Setting Up the Device Addresses
              2. 8.3.5.1.3.2.2 Setting Up COMM_CTRL[STACK_DEV] and [TOP_STACK]
              3. 8.3.5.1.3.2.3 Storing Device Address to OTP
            3. 8.3.5.1.3.3 Synchronize Daisy-Chain DLL
            4. 8.3.5.1.3.4 Ring Communication
          4. 8.3.5.1.4 Communication Timeout
            1. 8.3.5.1.4.1 Short Communication Timeout
            2. 8.3.5.1.4.2 Long Communication Timeout
          5. 8.3.5.1.5 Communication Debug Mode
          6. 8.3.5.1.6 Multidrop Configuration
          7. 8.3.5.1.7 SPI Master
          8. 8.3.5.1.8 SPI Loopback
        2. 8.3.5.2 Fault Handling
          1. 8.3.5.2.1 Fault Status Hierarchy
            1. 8.3.5.2.1.1 Debug Registers
          2. 8.3.5.2.2 Fault Masking and Reset
            1. 8.3.5.2.2.1 Fault Masking
            2. 8.3.5.2.2.2 Fault Reset
          3. 8.3.5.2.3 Fault Signaling
            1. 8.3.5.2.3.1 Fault Status Transmitting in ACTIVE Mode
            2. 8.3.5.2.3.2 Fault Status Transmitting in SLEEP Mode
            3. 8.3.5.2.3.3 Heartbeat and Fault Tone
        3. 8.3.5.3 Nonvolatile Memory
          1. 8.3.5.3.1 OTP Page Status
          2. 8.3.5.3.2 OTP Programming
        4. 8.3.5.4 Diagnostic Control/Status
          1. 8.3.5.4.1 Power Supplies Check
            1. 8.3.5.4.1.1 Power Supply Diagnostic Check
            2. 8.3.5.4.1.2 Power Supply BIST
          2. 8.3.5.4.2 Thermal Shutdown and Warning Check
            1. 8.3.5.4.2.1 Thermal Shutdown
            2. 8.3.5.4.2.2 Thermal Warning
          3. 8.3.5.4.3 Oscillators Watchdog
          4. 8.3.5.4.4 OTP Error Check
            1. 8.3.5.4.4.1 OTP CRC Test and Faults
            2. 8.3.5.4.4.2 OTP Margin Read
            3. 8.3.5.4.4.3 Error Check and Correct (ECC) OTP
          5. 8.3.5.4.5 OVUV Detection Check
            1. 8.3.5.4.5.1 Parity Check
            2. 8.3.5.4.5.2 OVUV DAC Check
            3. 8.3.5.4.5.3 OVUV Protector BIST
          6. 8.3.5.4.6 Diagnostic Through ADC Comparison
            1. 8.3.5.4.6.1 VS Voltage Measurement Check
            2. 8.3.5.4.6.2 Temperature Measurement Check
            3. 8.3.5.4.6.3 VS and AUX Open Wire Check
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 SHUTDOWN Mode
          1. 8.4.1.1.1 Exit SHUTDOWN Mode
          2. 8.4.1.1.2 Enter SHUTDOWN Mode
        2. 8.4.1.2 SLEEP Mode
          1. 8.4.1.2.1 Exit SLEEP Mode
          2. 8.4.1.2.2 Enter SLEEP Mode
        3. 8.4.1.3 ACTIVE Mode
          1. 8.4.1.3.1 Exit ACTIVE Mode
          2. 8.4.1.3.2 Enter ACTIVE Mode From SHUTDOWN Mode
          3. 8.4.1.3.3 Enter ACTIVE Mode From SLEEP Mode
      2. 8.4.2 Device Reset
      3. 8.4.3 Ping and Tone
        1. 8.4.3.1 Ping
        2. 8.4.3.2 Tone
        3. 8.4.3.3 Ping and Tone Propagation
    5. 8.5 Register Maps
      1. 8.5.1 OTP Shadow Register Summary
      2. 8.5.2 Read/Write Register Summary
      3. 8.5.3 Read-Only Register Summary
      4. 8.5.4 Register Field Descriptions
        1. 8.5.4.1  Device Addressing Setup
          1. 8.5.4.1.1 DIR0_ADDR_OTP
          2. 8.5.4.1.2 DIR1_ADDR_OTP
          3. 8.5.4.1.3 CUST_MISC1 through CUST_MISC8
          4. 8.5.4.1.4 DIR0_ADDR
          5. 8.5.4.1.5 DIR1_ADDR
        2. 8.5.4.2  Device ID and Scratch Pad
          1. 8.5.4.2.1 PARTID
          2. 8.5.4.2.2 DEV_REVID
          3. 8.5.4.2.3 DIE_ID1 through DIE_ID9
        3. 8.5.4.3  General Configuration and Control
          1. 8.5.4.3.1  DEV_CONF
          2. 8.5.4.3.2  PWR_TRANSIT_CONF
          3. 8.5.4.3.3  COMM_TIMEOUT_CONF
          4. 8.5.4.3.4  TX_HOLD_OFF
          5. 8.5.4.3.5  STACK_RESPONSE
          6. 8.5.4.3.6  COMM_CTRL
          7. 8.5.4.3.7  CONTROL1
          8. 8.5.4.3.8  CONTROL2
          9. 8.5.4.3.9  CUST_CRC_HI
          10. 8.5.4.3.10 CUST_CRC_LO
          11. 8.5.4.3.11 CUST_CRC_RSLT_HI
          12. 8.5.4.3.12 CUST_CRC_RSLT_LO
        4. 8.5.4.4  Operation Status
          1. 8.5.4.4.1 DIAG_STAT
          2. 8.5.4.4.2 ADC_STAT1
          3. 8.5.4.4.3 ADC_STAT2
          4. 8.5.4.4.4 GPIO_STAT
          5. 8.5.4.4.5 DEV_STAT
        5. 8.5.4.5  ADC Configuration and Control
          1. 8.5.4.5.1  ADC_CONF1
          2. 8.5.4.5.2  ADC_CONF2
          3. 8.5.4.5.3  MAIN_ADC_CAL1
          4. 8.5.4.5.4  MAIN_ADC_CAL2
          5. 8.5.4.5.5  AUX_ADC_CAL1
          6. 8.5.4.5.6  AUX_ADC_CAL2
          7. 8.5.4.5.7  CS_ADC_CAL1
          8. 8.5.4.5.8  CS_ADC_CAL2
          9. 8.5.4.5.9  ADC_CTRL1
          10. 8.5.4.5.10 ADC_CTRL2
          11. 8.5.4.5.11 ADC_CTRL3
        6. 8.5.4.6  ADC Measurement Results
          1. 8.5.4.6.1  VS16_HI/LO
          2. 8.5.4.6.2  VS15_HI/LO
          3. 8.5.4.6.3  VS14_HI/LO
          4. 8.5.4.6.4  VS13_HI/LO
          5. 8.5.4.6.5  VS12_HI/LO
          6. 8.5.4.6.6  VS11_HI/LO
          7. 8.5.4.6.7  VS10_HI/LO
          8. 8.5.4.6.8  VS9_HI/LO
          9. 8.5.4.6.9  VS8_HI/LO
          10. 8.5.4.6.10 VS7_HI/LO
          11. 8.5.4.6.11 VS6_HI/LO
          12. 8.5.4.6.12 VS5_HI/LO
          13. 8.5.4.6.13 VS4_HI/LO
          14. 8.5.4.6.14 VS3_HI/LO
          15. 8.5.4.6.15 VS2_HI/LO
          16. 8.5.4.6.16 VS1_HI/LO
          17. 8.5.4.6.17 CSAUX_HI/LO
          18. 8.5.4.6.18 TSREF_HI/LO
          19. 8.5.4.6.19 GPIO1_HI/LO
          20. 8.5.4.6.20 GPIO2_HI/LO
          21. 8.5.4.6.21 GPIO3_HI/LO
          22. 8.5.4.6.22 GPIO4_HI/LO
          23. 8.5.4.6.23 GPIO5_HI/LO
          24. 8.5.4.6.24 GPIO6_HI/LO
          25. 8.5.4.6.25 GPIO7_HI/LO
          26. 8.5.4.6.26 GPIO8_HI/LO
          27. 8.5.4.6.27 DIETEMP1_HI/LO
          28. 8.5.4.6.28 DIETEMP2_HI/LO
          29. 8.5.4.6.29 AUX_IN_HI/LO
          30. 8.5.4.6.30 AUX_GPIO_HI/LO
          31. 8.5.4.6.31 AUX_PWR_HI/LO
          32. 8.5.4.6.32 AUX_REFL_HI/LO
          33. 8.5.4.6.33 AUX_VBG2_HI/LO
          34. 8.5.4.6.34 AUX_AVAO_REF_HI/LO
          35. 8.5.4.6.35 AUX_AVDD_REF_HI/LO
          36. 8.5.4.6.36 AUX_OV_DAC_HI/LO
          37. 8.5.4.6.37 AUX_UV_DAC_HI/LO
          38. 8.5.4.6.38 AUX_VCM1_HI/LO
          39. 8.5.4.6.39 REFH_HI/LO
          40. 8.5.4.6.40 DIAG_MAIN_HI/LO
          41. 8.5.4.6.41 DIAG_AUX_HI/LO
          42. 8.5.4.6.42 CURRENT_HI/MID/LO
        7. 8.5.4.7  Protector Configuration and Control
          1. 8.5.4.7.1 OV_THRESH
          2. 8.5.4.7.2 UV_THRESH
          3. 8.5.4.7.3 UV_DISABLE1
          4. 8.5.4.7.4 UV_DISABLE2
          5. 8.5.4.7.5 OVUV_CTRL
        8. 8.5.4.8  GPIO Configuration
          1. 8.5.4.8.1 GPIO_CONF1
          2. 8.5.4.8.2 GPIO_CONF2
          3. 8.5.4.8.3 GPIO_CONF3
          4. 8.5.4.8.4 GPIO_CONF4
        9. 8.5.4.9  SPI Master
          1. 8.5.4.9.1 SPI_CONF
          2. 8.5.4.9.2 SPI_EXE
          3. 8.5.4.9.3 SPI_TX3, SPI_TX2, and SPI_TX1
          4. 8.5.4.9.4 SPI_RX3, SPI_RX2, and SPI_RX1
        10. 8.5.4.10 Diagnostic Control
          1. 8.5.4.10.1 DIAG_OTP_CTRL
          2. 8.5.4.10.2 DIAG_COMM_CTRL
          3. 8.5.4.10.3 DIAG_PWR_CTRL
          4. 8.5.4.10.4 DIAG_COMP_CTRL1
          5. 8.5.4.10.5 DIAG_COMP_CTRL2
          6. 8.5.4.10.6 DIAG_COMP_CTRL3
          7. 8.5.4.10.7 DIAG_COMP_CTRL4
          8. 8.5.4.10.8 DIAG_PROT_CTRL
        11. 8.5.4.11 Fault Configuration and Reset
          1. 8.5.4.11.1 FAULT_MSK1
          2. 8.5.4.11.2 FAULT_MSK2
          3. 8.5.4.11.3 FAULT_RST1
          4. 8.5.4.11.4 FAULT_RST2
        12. 8.5.4.12 Fault Status
          1. 8.5.4.12.1  FAULT_SUMMARY
          2. 8.5.4.12.2  FAULT_COMM1
          3. 8.5.4.12.3  FAULT_COMM2
          4. 8.5.4.12.4  FAULT_COMM3
          5. 8.5.4.12.5  FAULT_OTP
          6. 8.5.4.12.6  FAULT_SYS
          7. 8.5.4.12.7  FAULT_PROT1
          8. 8.5.4.12.8  FAULT_PROT2
          9. 8.5.4.12.9  FAULT_OV1
          10. 8.5.4.12.10 FAULT_OV2
          11. 8.5.4.12.11 FAULT_UV1
          12. 8.5.4.12.12 FAULT_UV2
          13. 8.5.4.12.13 FAULT_COMP_GPIO
          14. 8.5.4.12.14 FAULT_COMP_VSAUX1
          15. 8.5.4.12.15 FAULT_COMP_VSAUX2
          16. 8.5.4.12.16 FAULT_COMP_VSOW1
          17. 8.5.4.12.17 FAULT_COMP_VSOW2
          18. 8.5.4.12.18 FAULT_COMP_AUXOW1
          19. 8.5.4.12.19 FAULT_COMP_AUXOW2
          20. 8.5.4.12.20 FAULT_COMP_MISC
          21. 8.5.4.12.21 FAULT_PWR1
          22. 8.5.4.12.22 FAULT_PWR2
          23. 8.5.4.12.23 FAULT_PWR3
        13. 8.5.4.13 Debug Control and Status
          1. 8.5.4.13.1  DEBUG_CTRL_UNLOCK
          2. 8.5.4.13.2  DEBUG_COMM_CTRL1
          3. 8.5.4.13.3  DEBUG_COMM_CTRL2
          4. 8.5.4.13.4  DEBUG_COMM_STAT
          5. 8.5.4.13.5  DEBUG_UART_RC
          6. 8.5.4.13.6  DEBUG_UART_RR_TR
          7. 8.5.4.13.7  DEBUG_COMH_BIT
          8. 8.5.4.13.8  DEBUG_COMH_RC
          9. 8.5.4.13.9  DEBUG_COMH_RR_TR
          10. 8.5.4.13.10 DEBUG_COML_BIT
          11. 8.5.4.13.11 DEBUG_COML_RC
          12. 8.5.4.13.12 DEBUG_COML_RR_TR
          13. 8.5.4.13.13 DEBUG_UART_DISCARD
          14. 8.5.4.13.14 DEBUG_COMH_DISCARD
          15. 8.5.4.13.15 DEBUG_COML_DISCARD
          16. 8.5.4.13.16 DEBUG_UART_VALID_HI/LO
          17. 8.5.4.13.17 DEBUG_COMH_VALID_HI/LO
          18. 8.5.4.13.18 DEBUG_COML_VALID_HI/LO
          19. 8.5.4.13.19 DEBUG_OTP_SEC_BLK
          20. 8.5.4.13.20 DEBUG_OTP_DED_BLK
        14. 8.5.4.14 OTP Programming Control and Status
          1. 8.5.4.14.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
          2. 8.5.4.14.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
          3. 8.5.4.14.3 OTP_PROG_CTRL
          4. 8.5.4.14.4 OTP_ECC_TEST
          5. 8.5.4.14.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
          6. 8.5.4.14.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
          7. 8.5.4.14.7 OTP_PROG_STAT
          8. 8.5.4.14.8 OTP_CUST1_STAT
          9. 8.5.4.14.9 OTP_CUST2_STAT
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Base Device Application Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  PACK+ and FUSE Measurement
          2. 9.2.1.2.2  Insulation Measurement
          3. 9.2.1.2.3  LINK+/- Measurement
          4. 9.2.1.2.4  CHARGE+/– Measurement
          5. 9.2.1.2.5  Overcurrent Detection Scheme Using OVUV Comparators
          6. 9.2.1.2.6  Unused Pins
          7. 9.2.1.2.7  Current Sense Input
          8. 9.2.1.2.8  VPWR and External NPN
          9. 9.2.1.2.9  Power Supplies, Reference Input
          10. 9.2.1.2.10 GPIO For Thermistor Inputs
          11. 9.2.1.2.11 UART, NFAULT
          12. 9.2.1.2.12 Daisy-Chain Isolation
            1. 9.2.1.2.12.1 Devices Connected on the Same PCB
            2. 9.2.1.2.12.2 Devices Connected on Different PCBs
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Daisy Device Application Circuit
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Bypass Capacitors for Power Supplies and Reference
      3. 11.1.3 Voltage Sensing
      4. 11.1.4 Daisy-Chain Communication
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.1 Ground Planes

It is very important to establish a clean grounding scheme to ensure best performance of the device. There are three ground pins (AVSS, DVSS, CVSS) for the device’s internal power supplies and one ground reference (REFHM) for the precision reference. There are noisy grounds and quiet grounds that must be separated in the layout initially and re-joined together in a lower PCB layer. The external components (for example, bypass capacitors) must be tied to the proper grounding group if possible to keep the separation of noisy and quiet grounds apart.

  • AVSS ground:
    • Bypass capacitor for these pins: VPWR, VS0, AUX0, LDOIN and TSREF
    • Package PowerPAD
  • DVSS ground:
    • Bypass capacitor for DVDD
    • GPIO filter capacitor (if used). It can also connect to AVSS ground plane, if needed.
  • CVSS ground:
    • Bypass capacitor for CVDD
    • Bypass capacitors for COMHP/N, and COMLP/N
  • REFHM ground:
    • Bypass capacitor for REFHP
    • If possible, separate out REFHM from AVSS on the signal connection layer and re-connect REFHM to AVSS ground plane in the lower layer.

Even on a PCB layer that is mainly for signal routing, it is good practice to pour have a small island of ground pour if possible to provide a low-impedance ground, rather than simply a via through the ground trace to an lower ground plane.

GUID-20210818-SS0I-WJCD-FJNF-HNPJ1Q88DL5J-low.svg Figure 11-1 Grounding Layout Consideration