SLUSE48B May 2021 – November 2023 BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1
PRODUCTION DATA
Address | 0x0530 | |||||||
Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Name | RSVD | UART_TR | UART_RR | UART_RC | COMMCLR _DET | STOP_DET | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RSVD = | Reserved | |||||||
UART_TR = | Indicates a UART FAULT is detected when transmitting a response frame. Further details of the fault information are available in the DEBUG_UART_RR_TR register. 0 = No fault 1 = Fault | |||||||
UART_RR = | Indicates a UART FAULT is detected when receiving a response frame. Further details of the fault information are available in the DEBUG_UART_RR_TR register. 0 = No fault 1 = Fault | |||||||
UART_RC = | Indicates a UART FAULT is detected during receiving a command frame. Further details of the fault information are available in the DEBUG_UART_RC register. 0 = No fault 1 = Fault | |||||||
COMMCLR_DET = | A UART communication clear signal is detected. A detection of SLEEPtoACTIVE ping in ACTIVE or SLEEP mode or detection of WAKE pin in ACTIVE mode will also set this bit. 0 = No UART Clear 1 = UART Clear detected | |||||||
STOP_DET = | Indicates an unexpected STOP condition is received. A detection of SLEEPtoACTIVE signal in ACTIVE mode will also set this bit. 0 = No fault 1 = Fault |