SLUSE48B May 2021 – November 2023 BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER STATE TIMING | ||||||
tSU(WAKE_SHUT) | Startup from SHUTDOWN to ACTIVE mode | Base device: From the end of WAKE ping to the start of a forwading WAKE tone | 6 | 10 | ms | |
Stack device: From the end of a recevied WAKE tone to the start of a forwading WAKE tone | 6 | 10 | ms | |||
tSU(SLP2ACT) | Startup from SLEEP to ACTIVE mode (with SLEEP2ACTIVE ping/tone) | Base device: From the end of SLEEP2ACTIVE ping to the start of the forwarding SLEEP2ACTIVE tone | 230 | µs | ||
Stack device: From the end of SLEEP2ACTIVE tone to the start of the forwarding SLEEP2ACTIVE tone | 230 | µs | ||||
tSU(WAKE_SLP) | Startup from SLEEP to ACTIVE mode (with WAKE ping/tone) | Base device: From the end of WAKE ping to the start of a forwading WAKE tone | 1 | ms | ||
Stack device: From the end of a recevied WAKE tone to the start of a forwading WAKE tone | 1 | ms | ||||
tSLP | From ACTIVE to SLEEP mode | From receiving SLEEP entry condition to enter in SLEEP mode | 100 | µs | ||
tSHTDN | From ACTIVE to SLHUTDOWN mode | From receiving SHUTDOWN entry condition to enter in SHUTDOWN mode (all LDOs in 10% of their norminal value) | 20 | ms | ||
tRST | Reset time during ACTIVE mode | CONTROL1[SOFT_RST] = 1 is sent to a completion of the digital reset | 1 | ms | ||
tHWRST | The time device will be in HW reset, after HW reset ping/tone issued | 75 | ms | |||
SUPPLIES TIMING | ||||||
tTSREF_ON | TSREF ramp up time (10%-90%) | CTSREF = 1µF | 6 | ms | ||
tTSREF_OFF | TSREF ramp down time (90%-10%) | CTSREF = 1µF | 8 | ms | ||
PING SIGNAL TIMING | ||||||
tHLD_WAKE | WAKE ping low time on RX pin; no external load on CVDD | 2 | 2.5 | ms | ||
tHLD_SD | SHUTDOWN ping low time on RX pin; no external load on CVDD | 7 | 10 | ms | ||
tUART(StA) | SLEEPtoACTIVE ping low time on RX pin | 250 | 300 | µs | ||
tHLD_HWRST | HW_RESET ping low time on RX pin | 36 | ms | |||
COML and COMH (PULSE and TONE TIMING) | ||||||
tPW_DC | COMM: Pulse width of data (half bit time) for communiction | 250 | ns | |||
tRECLK_DC | COMM: data reclocking delay per device from COMH to COML or viceversa | 4 | 5 | µs | ||
tCOMTONE | Time between pulses of comm tones (HFO based). Comm Tones are WAKE, SLEEPtoACTIVE, SHUTDOWN, HWRST tones | 11 | 15 | µs | ||
tCOMMTONE_HI | The HIGH time of each comms pulse (HFO base) | 0.92 | 1 | 1.08 | µs | |
tCOMMTONE_LO | The LOW time of each comms pulse (HFO base) | 0.92 | 1 | 1.08 | µs | |
tFLTTONE | Time between pulses of FAULT Tone (LFO based). Applies to FAULT Tone and HEARTBEAT | 11.5 | µs | |||
tFLTTONE_HI | The HIGH time of each pulse of the tone couplete | 1 | µs | |||
tFLTTONE_LO | The LOW time of each pulse of the tone couplete | 1 | µs | |||
nWAKEDET | Number of pulses to detect as a WAKE tone | 60 | pulses | |||
nWAKE | Number of pulses to transit for a WAKE tone | 90 | pulses | |||
nSHDNDET | Number of pulses to detect as a SHUTDOWN tone | 180 | pulses | |||
nSHDN | Number of pulses to transit for a SHUTDOWN tone | 270 | pulses | |||
nSLPtoACTDET | Number of pulses to detect as a SLEEPtoACTIVE tone | 20 | pulses | |||
nSLPtoACT | Number of pulses to transit for a SLEEPtoACTIVE tone | 30 | pulses | |||
nHWRSTDET | Number of pulses to detect as a HW_RESET tone | 540 | pulses | |||
nHWRST | Number of pulses to transit for a HW_RESET tone | 810 | pulses | |||
nHBDET | HEARTBEAT: Number of pulses to detect as a valid tone | 20 | pulses | |||
nHB | HEARTBEAT: Number of pulses to transit for a tone | 30 | pulses | |||
tHB_PERIOD | HEARTBEAT: Period between HEARTBEAT Burst (from the beginning of a HEARTBEAT to the beginning of the next HEARTBEAT) | 360 | 400 | 440 | ms | |
tHB_TIMEOUT | HEARTBEAT: Timeout to considered as not receving HEARTBEAT | 0.9 | 1 | 1.1 | s | |
tHB_FAST | HEARTBEAT: If HEARTBEAT is received within this time, it is considered receving HEARTBEAT too fast | 200 | ms | |||
nFTONEDET | FAULT TONE: Number of pulses to detect as a valid tone | 60 | pulses | |||
nFTONE | FAULT TONE: Number of pulses to transit for a tone | 90 | pulses | |||
tFTONE_PERIOD | FAULT TONE: Period between FAULT TONE Burst (from the beginning of a FAULT TONE to the beginning of the next FAULT TONE) |
50 | ms | |||
tFTS_LATENCY | Fault Tone latency in Stack Device | From time a device receive the tone to the time the same device detects and generate its fault tone | 48 | µs | ||
tFTB_LATENCY | Fault Tone latency in Base Device | From the time a device receive the tone to the time the same device detects and asserts NFAULT | 24 | µs | ||
MAIN and AUX ADC TIMING | ||||||
tSAR_CONV | Single conversion time (both Main and AUX ADCs) | 8 | µs | |||
tMAIN_ADC_CYCLE | Single round robin cycle (Main ADC) | 192 | µs | |||
tAUX_ADC_CYCLE | Single round robin cycle (AUX ADC) | 192 | µs | |||
tAFE_SETTLE | Analog front end (Level shifters) settling time whenever device enter ACTIVE mode from SLEEP or SHUTDOWN | 4 | ms | |||
tCS_SETTLE | CS ADC settling time | 62 | µs | |||
tCS_REFRESH | Continious mode refresh rate | CS_DS[1:0] = 11 | 4.096 | ms | ||
tCS_REFRESH | Continious mode refresh rate | CS_DS[1:0] = 10 | 1.024 | ms | ||
tCS_REFRESH | Continious mode refresh rate | CS_DS[1:0] = 01 | 0.512 | ms | ||
tCS_REFRESH | Continious mode refresh rate | CS_DS[1:0] = 00 | 0.256 | ms | ||
tCS_CONV | Single conversion time on CS ADC | CS_DS[1:0] = 11 | 12.350 | ms | ||
CS_DS[1:0] = 10 | 3.134 | ms | ||||
CS_DS[1:0] = 01 | 1.598 | ms | ||||
CS_DS[1:0] = 00 | 0.83 | ms | ||||
tADC_ACC | This includes mux round robin, ADC conversions, and digital filters. | -1.5 | 1.5 | % | ||
BALANCING TIMING | ||||||
tBAL_ACC | Balancing timer accuracy | -5 | 5 | % | ||
HW COMPARATORS/PROTECTORS TIMING | ||||||
tOV_CYCLE | OV round robin cycle | 8 | ms | |||
tUV_CYCLE | UV round robin cycle | 8 | ms | |||
tOVUV_BIST_CYCLE | OV and UV BIST cycle | 21.8 | 23 | 24.2 | ms | |
tOT_CYCLE | OT round robin cycle | 4 | ms | |||
tUT_CYCLE | UT round robin cycle | 4 | ms | |||
tPWR_BIST_CYCLE | Time needed for the power supply BIST to complete after the power BIST go command | 10.9 | 11.5 | 12.1 | ms | |
tOTUT_BIST_CYCLE | OT and UT BIST cycle | 19 | 20 | 21 | ms | |
tHW_COMP_ACC | OV,UV,OT,UT comparators timing accuracy | -5 | 5 | % | ||
I/O TIMING (TX, RX, GPIO, NFAULT) | ||||||
tRISE | Rise Time | VCVDD > MIN VCVDD, CLOAD = 150pF, GPIO in output mode | 12 | ns | ||
tFALL | Fall Time (exclude NFAULT) | VCVDD > MIN VCVDD, CLOAD = 150pF, GPIO in output mode | 7 | ns | ||
tFALL_NFAULT | Fall Time on NFAULT | VCVDD > MIN VCVDD, CLOAD = 150pF, RPULLUP = 10kΩ | 100 | ns | ||
UART TIMING | ||||||
UARTBAUD | UART TX/RX Baud Rate | 1 | Mbps | |||
UARTERR_BAUD(RX) | UART RX baud rate error - requirement on the external host | -1 | 1 | % | ||
UARTERR_BAUD(TX) | UART TX baud rate error | -1.5 | 1.5 | % | ||
tUART(CLR) | UART Clear low time | 15 | 20 | bit period | ||
tUART(RX_HIGH) | After COMM CLEAR, wait this time before sending new frame | 1 | bit period | |||
OTP NVM TIMING | ||||||
tCRC_CUST | Time to complet a single cycle of CRC check on the customer OTP space | 175 | µs | |||
tCRC_FACT | Time to complet a single cycle of CRC check on the factory OTP space | 1.6 | ms | |||
SPI CONTROLLER TIMING | ||||||
fSCLK | SCLK frequency | 450 | 500 | 550 | kHz | |
tHIGH, tLOW | SCLK duty cycle | 50 | % | |||
tCS(HIGH) | CS HIGH latency time. Time from register write high to CS pin high | 4 | µs | |||
tCS(LOW) | CS LOW latency time. Time from register write low to CS pin low | 4 | µs | |||
tSU(POCI) | POCI input data setup time - requirement for slave device | POCI stable before SCLK transition | 100 | ns | ||
tHD(POCI) | POCI input dat hold time | POCI stable after SCLK transition | 0 | ns | ||
OSCILLATOR | ||||||
fHFO | High frequency oscillator | 31.52 | 32 | 32.48 | MHz | |
fLFO | Low frequency oscillator | 248.9 | 262 | 275.1 | kHz |