SBOS571C August   2011  – August 2018 BUF20800-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 General-call Reset and Power-up
      2. 7.3.2 Output Voltage
      3. 7.3.3 Output Latch
      4. 7.3.4 Programmable VCOM
      5. 7.3.5 REFH and REFL Input range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Replacement of Traditional Gamma Buffer
      2. 7.4.2 Dynamic Gamma Control
    5. 7.5 Programming
      1. 7.5.1 Two-wire Bus Overview
      2. 7.5.2 Data Rates
      3. 7.5.3 Read/Write Operations
        1. 7.5.3.1 Writing
        2. 7.5.3.2 Reading
      4. 7.5.4 Register Maps
        1. 7.5.4.1 Addressing the BUF20800-Q1
      5. 7.5.5 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 REFH and REFL Voltage Settings
      3. 8.2.3 Application Curves
      4. 8.2.4 Configuration for 20 Gamma Channels
      5. 8.2.5 Configuration for 22 Gamma Channels
      6. 8.2.6 The BUF20800-Q1 in Industrial Applications
      7. 8.2.7 Total TI Panel Solution
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PowerPAD Design Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DCP Package
38-Pin HTSSOP
TOP VIEW
BUF20800-Q1 po_dcp_bos571.gif
1. NC denotes no connection
2. GNDD and GNDA are internally connected and must be at the same voltage potential.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
A0 20 I Two-wire serial interface address select pin
GNDA 28 — Analog ground. Must be connected to digital ground GNDD.
11
GNDD 22 — Digital ground. Must be connected to analog ground GNDA.
LD 21 Output latch pin
NC 3 — No connection. Leave this pin floating.
4
35
36
OUT1 5 O DAC output 1
OUT2 6 O DAC output 2
OUT3 7 O DAC output 3
OUT4 8 O DAC output 4
OUT5 9 O DAC output 5
OUT6 10 O DAC output 6
OUT7 13 O DAC output 7
OUT8 14 O DAC output 8
OUT9 15 O DAC output 9
OUT10 23 O DAC output 10
OUT11 24 O DAC output 11
OUT12 25 O DAC output 12
OUT13 26 O DAC output 13
OUT14 29 O DAC output 14
OUT15 30 O DAC output 15
OUT16 31 O DAC output 16
OUT17 32 O DAC output 17
OUT18 33 O DAC output 18
REFH 2 I Reference voltage REFH input
REFH OUT 16 O Reference voltage REFH output
REFL 37 I Reference voltage REFL input
REFL OUT 34 O Reference voltage REFL output
SCL 18 I Serial clock input; open drain.
SDA 19 I/O Serial data I/O; open drain.
VCOMOUT1 38 O VCOM channel 1
VCOMOUT2 1 O VCOM channel 2
VS 12 I Analog supply
27
VSD 17 I Digital supply