SBOS998C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2 Functional Block Diagram

GUID-20210203-CA0I-CWB6-MXZZ-SF04T0571P98-low.gif Figure 8-1 Functional Block Diagram

Figure 8-1 shows an overview of the internal structure of the BUF802. The internal schematic of the BUF802 can be divided into the following 3 parts:

  • Input Stage, which consists of a low noise JFET and its biasing circuitry. The Input Stage can be configured in two modes, BF Mode and CL Mode. Choosing one of the two modes affects the circuit operation of the Input Stage. The Clamp and Output Stage operation are unaffected by the mode selection. Section 8.4 describes the two modes in greater detail.
  • Clamp Stage, which provides the following functions:
    1. Protects the input of the BUF802 against large input signal transients through diode clamps to VS- and CLH respectively.
    2. Ensures the output voltage of the BUF802 does not exceed the voltage at the CLH and CLL.
  • Output Stage, which tracks the JFET source voltage and is optimized to drive a 50 Ω and 100 Ω load while maintaining signal fidelity.