SWRS046I November   2006  – September 2018 CC1020

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Configuration
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  RF Transmit
    5. 4.5  RF Receive
    6. 4.6  RSSI / Carrier Sense
    7. 4.7  Intermediate Frequency (IF)
    8. 4.8  Crystal Oscillator
    9. 4.9  Frequency Synthesizer
    10. 4.10 Digital Inputs and Outputs
    11. 4.11 Current Consumption
    12. 4.12 Thermal Resistance Characteristics for VQFNP Package
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
      1. 5.3.1 Configuration Software
    4. 5.4  Microcontroller Interface
      1. 5.4.1 Configuration Interface
      2. 5.4.2 Signal Interface
      3. 5.4.3 PLL Lock Signal
    5. 5.5  4-wire Serial Configuration Interface
    6. 5.6  Signal Interface
      1. 5.6.1 Synchronous NRZ Mode
      2. 5.6.2 Transparent Asynchronous UART Mode
      3. 5.6.3 Synchronous Manchester Encoded Mode
        1. 5.6.3.1 Manchester Encoding and Decoding
    7. 5.7  Data Rate Programming
    8. 5.8  Frequency Programming
      1. 5.8.1 Dithering
    9. 5.9  Receiver
      1. 5.9.1  IF Frequency
      2. 5.9.2  Receiver Channel Filter Bandwidth
      3. 5.9.3  Demodulator, Bit Synchronizer, and Data Decision
      4. 5.9.4  Receiver Sensitivity Versus Data Rate and Frequency Separation
      5. 5.9.5  RSSI
      6. 5.9.6  Image Rejection Calibration
      7. 5.9.7  Blocking and Selectivity
      8. 5.9.8  Linear IF Chain and AGC Settings
      9. 5.9.9  AGC Settling
      10. 5.9.10 Preamble Length and Sync Word
      11. 5.9.11 Carrier Sense
      12. 5.9.12 Automatic Power-up Sequencing
      13. 5.9.13 Automatic Frequency Control
      14. 5.9.14 Digital FM
    10. 5.10 Transmitter
      1. 5.10.1 FSK Modulation Formats
      2. 5.10.2 Output Power Programming
      3. 5.10.3 TX Data Latency
      4. 5.10.4 Reducing Spurious Emission and Modulation Bandwidth
    11. 5.11 Input and Output Matching and Filtering
    12. 5.12 Frequency Synthesizer
      1. 5.12.1 VCO, Charge Pump and PLL Loop Filter
      2. 5.12.2 VCO and PLL Self-Calibration
      3. 5.12.3 PLL Turn-on Time Versus Loop Filter Bandwidth
      4. 5.12.4 PLL Lock Time Versus Loop Filter Bandwidth
    13. 5.13 VCO and LNA Current Control
    14. 5.14 Power Management
    15. 5.15 On-Off Keying (OOK)
    16. 5.16 Crystal Oscillator
    17. 5.17 Built-in Test Pattern Generator
    18. 5.18 Interrupt on Pin DCLK
      1. 5.18.1 Interrupt Upon PLL Lock
      2. 5.18.2 Interrupt Upon Received Signal Carrier Sense
    19. 5.19 PA_EN and LNA_EN Digital Output Pins
      1. 5.19.1 Interfacing an External LNA or PA
      2. 5.19.2 General Purpose Output Control Pins
      3. 5.19.3 PA_EN and LNA_EN Pin Drive
    20. 5.20 System Considerations and Guidelines
      1. 5.20.1 SRD Regulations
      2. 5.20.2 Narrowband Systems
      3. 5.20.3 Low Cost Systems
      4. 5.20.4 Battery Operated Systems
      5. 5.20.5 High Reliability Systems
      6. 5.20.6 Frequency Hopping Spread Spectrum Systems (FHSS)
    21. 5.21 Antenna Considerations
    22. 5.22 Configuration Registers
      1. 5.22.1 Memory
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
    2. 6.2 Design Requirements
      1. 6.2.1 Input and Output Matching
      2. 6.2.2 Bias Resistor
      3. 6.2.3 PLL Loop Filter
      4. 6.2.4 Crystal
      5. 6.2.5 Additional Filtering
      6. 6.2.6 Power Supply Decoupling and Filtering
    3. 6.3 PCB Layout Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9.6 Image Rejection Calibration

For perfect image rejection, the phase and gain of the “I” and “Q” parts of the analog RX chain must be perfectly matched. To improve the image rejection, the “I” and “Q” phase and gain difference can be fine-tuned by adjusting the PHASE_COMP and GAIN_COMP registers. This allows compensation for process variations and other nonidealities. The calibration is done by injecting a signal at the image frequency, and adjusting the phase and gain difference for minimum RSSI value.

During image rejection calibration, an unmodulated carrier should be applied at the image frequency (614.4 kHz below the desired channel). No signal should be present in the desired channel. The signal level should be 50 to 60 dB above the sensitivity in the desired channel, but the optimum level will vary from application to application. Too large input level gives poor results due to limited linearity in the analog IF chain, while too low input level gives poor results due to the receiver noise floor.

For best RSSI accuracy, use AGC_AVG[1:0] = 11 during image rejection calibration (RSSI value is averaged over 16 filter output samples). The RSSI register update rate then equals the receiver channel bandwidth (set in FILTER register) divided by 8, as the filter output rate is twice the receiver channel bandwidth. This gives the minimum waiting time between RSSI register reads (0.5 ms is used below). TI recommends the following image calibration procedure:

  1. Define 3 variables: XP = 0, XG = 0 and DX = 64. Go to step 3.
  2. Set DX = DX/2.
  3. Write XG to GAIN_COMP register.
  4. If XP + 2 × DX < 127, then write XP + 2 × DX to PHASE_COMP register else write 127 to PHASE_COMP register.
  5. Wait at least 3 ms. Measure signal strength Y4 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  6. Write XP+DX to PHASE_COMP register.
  7. Wait at least 3 ms. Measure signal strength Y3 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  8. Write XP to PHASE_COMP register.
  9. Wait at least 3 ms. Measure signal strength Y2 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  10. Write XP-DX to PHASE_COMP register.
  11. Wait at least 3 ms. Measure signal strength Y1 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  12. Write XP – 2 × DX to PHASE_COMP register.
  13. Wait at least 3 ms. Measure signal strength Y0 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  14. Set AP = 2 × (Y0 – Y2 + Y4) – (Y1 + Y3).
  15. If AP > 0 then set DP = ROUND ( 7 × DX × (2 × (Y0 – Y4) + Y1 – Y3) / (10 × AP)) else if Y0 + Y1 > Y3 + Y4 then set DP = DX else set DP = –DX.
  16. If DP > DX then set DP = DX else if DP < –DX then set DP = –DX.
  17. Set XP = XP + DP.
  18. Write XP to PHASE_COMP register.
  19. If XG + 2 × DX < 127 then write XG + 2 × DX to GAIN_COMP register else write 127 to GAIN_COMP register.
  20. Wait at least 3 ms. Measure signal strength Y4 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  21. Write XG + DX to GAIN_COMP register.
  22. Wait at least 3 ms. Measure signal strength Y3 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  23. Write XG to GAIN_COMP register.
  24. Wait at least 3 ms. Measure signal strength Y2 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  25. Write XG – DX to GAIN_COMP register.
  26. Wait at least 3 ms. Measure signal strength Y1 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  27. Write XG – 2 × DX to GAIN_COMP register.
  28. Wait at least 3 ms. Measure signal strength Y0 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
  29. Set AG = 2 × (Y0 – Y2 + Y4) – (Y1 + Y3).
  30. If AG > 0 then set DG = ROUND (7 × DX × (2 × (Y0 – Y4) + Y1 – Y3) / (10 × AG) else if Y0 + Y1 > Y3 + Y4 then set DG = DX else set DG = –DX.
  31. If DG > DX then set DG = DX else if DG < –DX then set DG = –DX
  32. Set XG = XG + DG.
  33. If DX > 1 then go to step 2.
  34. Write XP to PHASE_COMP register and XG to GAIN_COMP register.

If repeated calibration gives varying results, try to change the input level or increase the number of RSSI reads N. A good starting point is N = 8. As accuracy is more important in the last fine-calibration steps, it can be worthwhile to increase N for each loop iteration.

For high frequency deviation and high data rates (typically ≥ 76.8 kBaud), the analog filter succeeding the mixer must be bypassed by setting FILTER_BYPASS = 1 in the FILTER register. In this case the image rejection is degraded.

The image rejection is reduced for low supply voltages (typically < 2.5 V) when operating in the 402- to 470- MHz frequency range.