SWRS046I November   2006  – September 2018 CC1020

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Configuration
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  RF Transmit
    5. 4.5  RF Receive
    6. 4.6  RSSI / Carrier Sense
    7. 4.7  Intermediate Frequency (IF)
    8. 4.8  Crystal Oscillator
    9. 4.9  Frequency Synthesizer
    10. 4.10 Digital Inputs and Outputs
    11. 4.11 Current Consumption
    12. 4.12 Thermal Resistance Characteristics for VQFNP Package
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
      1. 5.3.1 Configuration Software
    4. 5.4  Microcontroller Interface
      1. 5.4.1 Configuration Interface
      2. 5.4.2 Signal Interface
      3. 5.4.3 PLL Lock Signal
    5. 5.5  4-wire Serial Configuration Interface
    6. 5.6  Signal Interface
      1. 5.6.1 Synchronous NRZ Mode
      2. 5.6.2 Transparent Asynchronous UART Mode
      3. 5.6.3 Synchronous Manchester Encoded Mode
        1. 5.6.3.1 Manchester Encoding and Decoding
    7. 5.7  Data Rate Programming
    8. 5.8  Frequency Programming
      1. 5.8.1 Dithering
    9. 5.9  Receiver
      1. 5.9.1  IF Frequency
      2. 5.9.2  Receiver Channel Filter Bandwidth
      3. 5.9.3  Demodulator, Bit Synchronizer, and Data Decision
      4. 5.9.4  Receiver Sensitivity Versus Data Rate and Frequency Separation
      5. 5.9.5  RSSI
      6. 5.9.6  Image Rejection Calibration
      7. 5.9.7  Blocking and Selectivity
      8. 5.9.8  Linear IF Chain and AGC Settings
      9. 5.9.9  AGC Settling
      10. 5.9.10 Preamble Length and Sync Word
      11. 5.9.11 Carrier Sense
      12. 5.9.12 Automatic Power-up Sequencing
      13. 5.9.13 Automatic Frequency Control
      14. 5.9.14 Digital FM
    10. 5.10 Transmitter
      1. 5.10.1 FSK Modulation Formats
      2. 5.10.2 Output Power Programming
      3. 5.10.3 TX Data Latency
      4. 5.10.4 Reducing Spurious Emission and Modulation Bandwidth
    11. 5.11 Input and Output Matching and Filtering
    12. 5.12 Frequency Synthesizer
      1. 5.12.1 VCO, Charge Pump and PLL Loop Filter
      2. 5.12.2 VCO and PLL Self-Calibration
      3. 5.12.3 PLL Turn-on Time Versus Loop Filter Bandwidth
      4. 5.12.4 PLL Lock Time Versus Loop Filter Bandwidth
    13. 5.13 VCO and LNA Current Control
    14. 5.14 Power Management
    15. 5.15 On-Off Keying (OOK)
    16. 5.16 Crystal Oscillator
    17. 5.17 Built-in Test Pattern Generator
    18. 5.18 Interrupt on Pin DCLK
      1. 5.18.1 Interrupt Upon PLL Lock
      2. 5.18.2 Interrupt Upon Received Signal Carrier Sense
    19. 5.19 PA_EN and LNA_EN Digital Output Pins
      1. 5.19.1 Interfacing an External LNA or PA
      2. 5.19.2 General Purpose Output Control Pins
      3. 5.19.3 PA_EN and LNA_EN Pin Drive
    20. 5.20 System Considerations and Guidelines
      1. 5.20.1 SRD Regulations
      2. 5.20.2 Narrowband Systems
      3. 5.20.3 Low Cost Systems
      4. 5.20.4 Battery Operated Systems
      5. 5.20.5 High Reliability Systems
      6. 5.20.6 Frequency Hopping Spread Spectrum Systems (FHSS)
    21. 5.21 Antenna Considerations
    22. 5.22 Configuration Registers
      1. 5.22.1 Memory
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
    2. 6.2 Design Requirements
      1. 6.2.1 Input and Output Matching
      2. 6.2.2 Bias Resistor
      3. 6.2.3 PLL Loop Filter
      4. 6.2.4 Crystal
      5. 6.2.5 Additional Filtering
      6. 6.2.6 Power Supply Decoupling and Filtering
    3. 6.3 PCB Layout Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.22.1 Memory

Table 5-17 MAIN Register (00h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
MAIN[7] RXTX — — RX/TX switch, 0: RX , 1: TX
MAIN[6] F_REG — — Selection of Frequency Register, 0: Register A, 1: Register B
MAIN[5:4] PD_MODE[1:0] — — Power down mode

0 (00): Receive Chain in power-down in TX, PA in power-down in RX
1 (01): Receive Chain and PA in power down in both TX and RX
2 (10): Individual modules can be put in power down by programming the POWERDOWN register
3 (11): Automatic power-up sequencing is activated
(see Table 5-18)
MAIN[3] FS_PD — H Power Down of Frequency Synthesizer
MAIN[2] XOSC_PD — H Power Down of Crystal Oscillator Core
MAIN[1] BIAS_PD — H Power Down of BIAS (Global Current Generator) and Crystal Oscillator Buffer
MAIN[0] RESET_N — L Reset, active low. Writing RESET_N low will write default values to all other registers than MAIN. Bits in MAIN do not have a default value and will be written directly through the configuration interface. Must be set high to complete reset.

Table 5-18 MAIN Register (00h) When Using Automatic Power-up Sequencing
(RXTX = 0, PD_MODE[1:0] =11)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
MAIN[7] RXTX — — Automatic power-up sequencing only works in RX (RXTX=0)
MAIN[6] F_REG — — Selection of Frequency Register, 0: Register A, 1: Register B
MAIN[5:4] PD_MODE[1:0] — H Set PD_MODE[1:0]=3 (11) to enable sequencing
MAIN[3:2] SEQ_CAL[1:0] — — Controls PLL calibration before re-entering power down

0: Never perform PLL calibration as part of sequence
1: Always perform PLL calibration at end of sequence
2: Perform PLL calibration at end of every 16th sequence
3: Perform PLL calibration at end of every 256th sequence
MAIN[1] SEQ_PD — ↑ ↑1: Put the chip in power down and wait for start of new power-up sequence
MAIN[0] RESET_N — L Reset, active low. Writing RESET_N low will write default values to all other registers than MAIN. Bits in MAIN do not have a default value and will be written directly through the configuration interface. Must be set high to complete reset.

Table 5-19 INTERFACE Register (01h)(1)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
INTERFACE[7] XOSC_BYPASS 0 H Bypass internal crystal oscillator, use external clock

0: Internal crystal oscillator is used, or external sine wave fed through a coupling capacitor
1: Internal crystal oscillator in power down, external clock with rail-to-rail swing is used
INTERFACE[6] SEP_DI_DO 0 H Use separate pin for RX data output

0: DIO is data output in RX and data input in TX. LOCK pin is available (Normal operation).
1: DIO is always input, and a separate pin is used for RX data output (synchronous mode: LOCK pin, asynchronous mode: DCLK pin).

If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING register then negative transitions on DIO is used to start power-up sequencing when PD_MODE=3 (power-up sequencing is enabled).
INTERFACE[5] DCLK_LOCK 0 H Gate DCLK signal with PLL lock signal in synchronous mode
Only applies when PD_MODE = "01"

0: DCLK is always 1
1: DCLK is always 1 unless PLL is in lock
INTERFACE[4] DCLK_CS 0 H Gate DCLK signal with carrier sense indicator in synchronous mode
Use when receive chain is active (in power up)
Always set to 0 in TX mode.

0: DCLK is independent of carrier sense indicator.
1: DCLK is always 1 unless carrier sense is indicated
INTERFACE[3] EXT_PA 0 H Use PA_EN pin to control external PA

0: PA_EN pin always equals EXT_PA_POL bit
1: PA_EN pin is asserted when internal PA is turned on
INTERFACE[2] EXT_LNA 0 H Use LNA_EN pin to control external LNA

0: LNA_EN pin always equals EXT_LNA_POL bit
1: LNA_EN pin is asserted when internal LNA is turned on
INTERFACE[1] EXT_PA_POL 0 H Polarity of external PA control

0: PA_EN pin is "0" when activating external PA
1: PA_EN pin is “1” when activating external PA
INTERFACE[0] EXT_LNA_POL 0 H Polarity of external LNA control

0: LNA_EN pin is “0” when activating external LNA
1: LNA_EN pin is “1” when activating external LNA
(1) If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2:0]=001.

Table 5-20 RESET Register (02h)(1)(2)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
RESET[7] ADC_RESET_N 0 L Reset ADC control logic
RESET[6] AGC_RESET_N 0 L Reset AGC (VGA control) logic
RESET[5] GAUSS_RESET_N 0 L Reset Gaussian data filter
RESET[4] AFC_RESET_N 0 L Reset AFC / FSK decision level logic
RESET[3] BITSYNC_RESET_N 0 L Reset modulator, bit synchronization logic and PN9 PRBS generator
RESET[2] SYNTH_RESET_N 0 L Reset digital part of frequency synthesizer
RESET[1] SEQ_RESET_N 0 L Reset power-up sequencing logic
RESET[0] CAL_LOCK_RESET_N 0 L Reset calibration logic and lock detector
(1) For reset of the CC1020 device, write RESET_N=0 in the MAIN register. The reset register should not be used during normal operation.
(2) Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant digital clocks must be running for the resetting to complete. After writing to the RESET register, the user should verify that all reset operations have been completed, by reading the RESET_DONE status register (41h) until all bits equal 1.

Table 5-21 SEQUENCING Register (03h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
SEQUENCING[7] SEQ_PSEL 1 H Use PSEL pin to start sequencing

0: PSEL pin does not start sequencing. Negative transitions on DIO starts power-up sequencing if SEP_DI_DO=1.
1: Negative transitions on the PSEL pin will start power-up sequencing
SEQUENCING[6:4] RX_WAIT[2:0] 0 — Waiting time from PLL enters lock until RX power up

0: Wait for approx. 32 ADC_CLK periods (26 μs)
1: Wait for approx. 44 ADC_CLK periods (36 μs)
2: Wait for approx. 64 ADC_CLK periods (52 μs)
3: Wait for approx. 88 ADC_CLK periods (72 μs)
4: Wait for approx. 128 ADC_CLK periods (104 μs)
5: Wait for approx. 176 ADC_CLK periods (143 μs)
6: Wait for approx. 256 ADC_CLK periods (208 μs)
7: No additional waiting time before RX power up
SEQUENCING[3:0] CS_WAIT[3:0] 10 — Waiting time for carrier sense from RX power up

0: Wait 20 FILTER_CLK periods before power down
1: Wait 22 FILTER_CLK periods before power down
2: Wait 24 FILTER_CLK periods before power down
3: Wait 26 FILTER_CLK periods before power down
4: Wait 28 FILTER_CLK periods before power down
5: Wait 30 FILTER_CLK periods before power down
6: Wait 32 FILTER_CLK periods before power down
7: Wait 36 FILTER_CLK periods before power down
8: Wait 40 FILTER_CLK periods before power down
9: Wait 44 FILTER_CLK periods before power down
10: Wait 48 FILTER_CLK periods before power down
11: Wait 52 FILTER_CLK periods before power down
12: Wait 56 FILTER_CLK periods before power down
13: Wait 60 FILTER_CLK periods before power down
14: Wait 64 FILTER_CLK periods before power down
15: Wait 72 FILTER_CLK periods before power down

Table 5-22 FREQ_2A Register (04h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FREQ_2A[7:0] FREQ_A[22:15] 131 — 8 MSB of frequency control word A

Table 5-23 FREQ_1A Register (05h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FREQ_1A[7:0] FREQ_1A[7:0] 177 — Bit 15 to 8 of frequency control word A

Table 5-24 FREQ_0A Register (06h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FREQ_0A[7:1] FREQ_A[6:0] 124 — 7 LSB of frequency control word A
FREQ_0A[0] DITHER_A 1 H Enable dithering for frequency A

Table 5-25 CLOCK_A Register (07h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
CLOCK_A[7:5] REF_DIV_A[2:0] 2 — Reference frequency divisor (A):

0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8

It is recommended to use the highest possible reference clock frequency that allows the desired Baud rate.
CLOCK_A[4:2] MCLK_DIV1_A[2:0] 4 — Modem clock divider 1 (A):

0: Divide by 2.5
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5 × 3)
4: Divide by 12.5 (2.5 × 5)
5: Divide by 40 (2.5 × 16)
6: Divide by 48 (3 × 16)
7: Divide by 64 (4 × 16)
CLOCK_A[1:0] MCLK_DIV2_A[1:0] 0 — Modem clock divider 2 (A):

0: Divide by 1
1: Divide by 2
2: Divide by 4
3: Divide by 8

MODEM_CLK frequency is FREF frequency divided by the product of divider 1 and divider 2.

Baud rate is MODEM_CLK frequency divided by 8.

Table 5-26 FREQ_2B Register (08h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FREQ_2B[7:0] FREQ_B[22:15] 131 — 8 MSB of frequency control word B

Table 5-27 FREQ_1B Register (09h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FREQ_1B[7:0] FREQ_B[14:7] 189 — 8 MSB of frequency control word B

Table 5-28 FREQ_0B Register (0Ah)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FREQ_0B[7:1] FREQ_B[6:0] 124 — 7 LSB of frequency control word B
FREQ_0B[0] DITHER_B 1 H Enable dithering for frequency B

Table 5-29 CLOCK_B Register (0Bh)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
CLOCK_B[7:5] REF_DIV_B[2:0] 2 — Reference frequency divisor (B):

0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8
CLOCK_B[4:2] MCLK_DIV1_B[2:0] 4 — Modem clock divider 1 (B):

0: Divide by 2.5
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5 × 3)
4: Divide by 12.5 (2.5 × 5)
5: Divide by 40 (2.5 × 16)
6: Divide by 48 (3 × 16)
7: Divide by 64 (4 × 16)
CLOCK_B[1:0] MCLK_DIV2_B[1:0] 0 — Modem clock divider 2 (B):

0: Divide by 1
1: Divide by 2
2: Divide by 4
3: Divide by 8

MODEM_CLK frequency is FREF frequency divided by the product of divider 1 and divider 2.

Baud rate is MODEM_CLK frequency divided by 8.

Table 5-30 VCO Register (0Ch)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
VCO[7:4] VCO_CURRENT_A[3:0] 8 — Control of current in VCO core for frequency A

0 : 1.4 mA current in VCO core
1 : 1.8 mA current in VCO core
2 : 2.1 mA current in VCO core
3 : 2.5 mA current in VCO core
4 : 2.8 mA current in VCO core
5 : 3.2 mA current in VCO core
6 : 3.5 mA current in VCO core
7 : 3.9 mA current in VCO core
8 : 4.2 mA current in VCO core
9 : 4.6 mA current in VCO core
10 : 4.9 mA current in VCO core
11 : 5.3 mA current in VCO core
12 : 5.6 mA current in VCO core
13 : 6.0 mA current in VCO core
14 : 6.4 mA current in VCO core
15 : 6.7 mA current in VCO core

Recommended setting: VCO_CURRENT_A=4
VCO[3:0] VCO_CURRENT_B[3:0] 8 —

Control of current in VCO core for frequency B

The current steps are the same as for VCO_CURRENT_A

Recommended setting: VCO_CURRENT_B=4

Table 5-31 MODEM Register (0Dh)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
MODEM[7] — 0 — Reserved, write 0
MODEM[6:4] ADC_DIV[2:0] 3 — ADC clock divisor(1)

0: Not supported
1: ADC frequency = XOSC frequency / 4
2: ADC frequency = XOSC frequency / 6
3: ADC frequency = XOSC frequency / 8
4: ADC frequency = XOSC frequency / 10
5: ADC frequency = XOSC frequency / 12
6: ADC frequency = XOSC frequency / 14
7: ADC frequency = XOSC frequency / 16
MODEM[3] — 0 — Reserved, write 0
MODEM[2] PN9_ENABLE 0 H Enable scrambling of TX and RX with PN9 pseudo-random bit sequence

0: PN9 scrambling is disabled
1: PN9 scrambling is enabled (x9 + x5 + 1)

The PN9 pseudo-random bit sequence can be used for BER testing by only transmitting zeros, and then counting the number of received ones.
MODEM[1:0] DATA_FORMAT[1:0] 0 — Modem data format

0 (00): NRZ operation
1 (01): Manchester operation
2 (10): Transparent asynchronous UART operation, set DCLK=0
3 (11): Transparent asynchronous UART operation, set DCLK=1
(1) The intermediate frequency should be as close to 307.2 kHz as possible. ADC clock frequency is always 4 times the intermediate frequency and should therefore be as close to 1.2288 MHz as possible.

Table 5-32 DEVIATION Register (0Eh)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
DEVIATION[7] TX_SHAPING 1 H Enable Gaussian shaping of transmitted data

Recommended setting: TX_SHAPING=1
DEVIATION[6:4] TXDEV_X[2:0] 6 — Transmit frequency deviation exponent
DEVIATION [3:0] TXDEV_M[3:0] 8 — Transmit frequency deviation mantissa

Deviation in 402 to 470 MHz band:

FREF × XDEV_M × 2(TXDEV_X−16)

Deviation in 804 to 930 MHz band:

FREF × TXDEV_M × 2(TXDEV_X−15)

On-off-keying (OOK) is used in RX/TX if TXDEV_M[3:0]=0

To find TXDEV_M given the deviation and TXDEV_X:

TXDEV_M = deviation × 2(16−TXDEV_X) / FREF

in 402 to 470 MHz band,

TXDEV_M = deviation × 2(15−TXDEV_X) / FREF

in 804 to 930 MHz band,

Decrease TXDEV_X and try again if TXDEV_M < 8.
Increase TXDEV_X and try again if TXDEV_M ≥ 16.

Table 5-33 AFC_CONTROL Register (0Fh)(1)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
AFC_CONTROL[7:6] SETTLING[1:0] 2 — Controls AFC settling time versus accuracy

0: AFC off; zero average frequency is used in demodulator
1: Fastest settling; frequency averaged over 1 0/1 bit pair
2: Medium settling; frequency averaged over 2 0/1 bit pairs
3: Slowest settling; frequency averaged over 4 0/1 bit pairs

Recommended setting:

AFC_CONTROL=3 for higher accuracy unless it is essential to have the fastest settling time when transmission starts after RX is activated.
AFC_CONTROL[5:4] RXDEV_X[1:0] 1 — RX frequency deviation exponent
AFC_CONTROL[3:0] RXDEV_M[3:0] 12 — RX frequency deviation mantissa

Expected RX deviation should be:

Baud rate × RXDEV_M × 2(RXDEV_X−3) / 3

To find RXDEV_M given the deviation and RXDEV_X:

RXDEV_M = 3 × deviation × 2(3−RXDEV_X) / Baud rate

Decrease RXDEV_X and try again if RXDEV_M < 8.

Increase RXDEV_X and try again if RXDEV_M ≥ 16.
(1) The RX frequency deviation should be close to half the TX frequency deviation for GFSK at 100 kBaud data rate and below. The RX frequency deviation should be close to the TX frequency deviation for FSK and for GFSK at 100 kBaud data rate and above.

Table 5-34 FILTER Register (10h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FILTER[7] FILTER_BYPASS 0 H Bypass analog image rejection / anti-alias filter. Set to 1 for increased dynamic range at high Baud rates.
Recommended setting:

FILTER_BYPASS=0 below 76.8 kBaud,

FILTER_BYPASS=1 for 76.8 kBaud and up.
FILTER[6:5] DEC_SHIFT[1:0] 0 — Number of extra bits to shift decimator input (may improve filter accuracy and lower power consumption).

Recommended settings:

DEC_SHIFT=0 when DEC_DIV ≤1
(receiver channel bandwidth ≥ 153.6 kHz),

DEC_SHIFT=1 when optimized sensitivity and 1< DEC_DIV < 24
(12.29 kHz < receiver channel bandwidth < 153.6 kHz),

DEC_SHIFT=2 when optimized selectivity and DEC_DIV ≥ 24
(receiver channel bandwidth ≤12.29 kHz)
FILTER[4:0] DEC_DIV[4:0] 0 — Decimation clock divisor

0: Decimation clock divisor = 1, 307.2 kHz channel filter BW.
1: Decimation clock divisor = 2, 153.6 kHz channel filter BW.
…
30: Decimation clock divisor = 31, 9.91 kHz channel filter BW.
31: Decimation clock divisor = 32, 9.6 kHz channel filter BW.

Channel filter bandwidth is 307.2 kHz divided by the decimation clock divisor.

Table 5-35 VGA1 Register (11h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
VGA1[7:6] CS_SET[1:0] 1 — Sets the number of consecutive samples at or above carrier sense level before carrier sense is indicated (for example, on LOCK pin)

0: Set carrier sense after first sample at or above carrier sense level
1: Set carrier sense after second sample at or above carrier sense level
2: Set carrier sense after third sample at or above carrier sense level
3: Set carrier sense after fourth sample at or above carrier sense level

Increasing CS_SET reduces the number of “false” carrier sense events due to noise at the expense of increased carrier sense response time.
VGA1[5] CS_RESET 1 — Sets the number of consecutive samples below carrier sense level before carrier sense indication (for example, on lock pin) is reset

0: Carrier sense is reset after first sample below carrier sense level
1: Carrier sense is reset after second sample below carrier sense level

Recommended setting: CS_RESET=1 in order to reduce the chance of losing carrier sense due to noise.
VGA1[4:2] VGA_WAIT[2:0] 1 — Controls how long AGC, bit synchronization, AFC and RSSI levels are frozen after VGA gain is changed when frequency is changed between A and B or PLL has been out of lock or after RX power up

0: Freeze operation for 16 filter clocks, 8/(filter BW) seconds
1: Freeze operation for 20 filter clocks, 10/(filter BW) seconds
2: Freeze operation for 24 filter clocks, 12/(filter BW) seconds
3: Freeze operation for 28 filter clocks, 14/(filter BW) seconds
4: Freeze operation for 32 filter clocks, 16/(filter BW) seconds
5: Freeze operation for 40 filter clocks, 20/(filter BW) seconds
6: Freeze operation for 48 filter clocks, 24/(filter BW) seconds
7: Freeze present levels unconditionally
VGA1[1:0] VGA_FREEZE[1:0] 1 — Controls the additional time AGC, bit synchronization, AFC and RSSI levels are frozen when frequency is changed between A and B or PLL has been out of lock or after RX power up

0: Freeze levels for approx. 16 ADC_CLK periods (13 µs)
1: Freeze levels for approx. 32 ADC_CLK periods (26 µs)
2: Freeze levels for approx. 64 ADC_CLK periods (52 µs)
3: Freeze levels for approx. 128 ADC_CLK periods (104 µs)

Table 5-36 VGA2 Register (12h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
VGA2[7] LNA2_MIN 0 — Minimum LNA2 setting used in VGA

0: Minimum LNA2 gain
1: Medium LNA2 gain

Recommended setting: LNA2_MIN=0 for best selectivity.
VGA2[6] LNA2_MAX 1 — Maximum LNA2 setting used in VGA

0: Medium LNA2 gain
1: Maximum LNA2 gain

Recommended setting: LNA2_MAX=1 for best sensitivity.
VGA2[5:4] LNA2_SETTING[1:0] 3 — Selects at what VGA setting the LNA gain should be changed

0: Apply LNA2 change below min. VGA setting.
1: Apply LNA2 change at approx. 1/3 VGA setting (around VGA setting 10).
2: Apply LNA2 change at approx. 2/3 VGA setting (around VGA setting 19).
3: Apply LNA2 change above max. VGA setting.

Recommended setting:

LNA2_SETTING=0 if VGA_SETTING<10, LNA2_SETTING=1 otherwise.

If LNA2_MIN=1 and LNA2_MAX=0, then the LNA2 setting is controlled by LNA2_SETTING:

0: Between medium and maximum LNA2 gain
1: Minimum LNA2 gain
2: Medium LNA2 gain
3: Maximum LNA2 gain
VGA2[3] AGC_DISABLE 0 H Disable AGC

0: AGC is enabled
1: AGC is disabled (VGA_SETTING determines VGA gain)

Recommended setting: AGC_DISABLE=0 for good dynamic range.
VGA2[2] AGC_HYSTERESIS 1 H Enable AGC hysteresis

0: No hysteresis. Immediate gain change for smallest up/down step
1: Hysteresis enabled. Two samples in a row must indicate gain change for smallest up or down step

Recommended setting: AGC_HYSTERESIS=1.
VGA2[1:0] AGC_AVG[1:0] 1 — Sets how many samples that are used to calculate average output magnitude for AGC/RSSI.

0: Magnitude is averaged over 2 filter output samples
1: Magnitude is averaged over 4 filter output samples
2: Magnitude is averaged over 8 filter output samples
3: Magnitude is averaged over 16 filter output samples

Recommended setting: AGC_AVG=1.

For best AGC/RSSI accuracy AGC_AVG=3.

For automatic power-up sequencing, the AGC_AVG and CS_SET values must be chosen so that carrier sense is available in time to be detected before the chip re-enters power down.

Table 5-37 VGA3 Register (13h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
VGA3[7:5] VGA_DOWN[2:0] 1 — Decides how much the signal strength must be above CS_LEVEL+VGA_UP before VGA gain is decreased. Based on the calculated internal strength level, which has an LSB resolution of 1.5 dB.

0: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP + 3
1: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP + 4
…
6: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP + 9
7: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP + 10

See Figure 5-15 for an explanation of the relationship between RSSI, AGC and carrier sense settings.
VGA3[4:0] VGA_SETTING[4:0] 24 H VGA setting to be used when receive chain is turned on

This is also the maximum gain that the AGC is allowed to use.

See Figure 5-15 for an explanation of the relationship between RSSI, AGC and carrier sense settings.

Table 5-38 VGA4 Register (14h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
VGA4[7:5] VGA_UP[2:0] 1 — Decides the level where VGA gain is increased if it is not already at the maximum set by VGA_SETTING. Based on the calculated internal strength level, which has an LSB resolution of 1.5 dB.

0: Gain is increased when signal is below CS_LEVEL + 8
1: Gain is increased when signal is below CS_LEVEL+ 8 + 1
…
6: Gain is increased when signal is below CS_LEVEL+ 8 + 6
7: Gain is increased when signal below CS_LEVEL+ 8 + 7

See Figure 5-15 for an explanation of the relationship between RSSI, AGC and carrier sense settings.
VGA4[4:0] CS_LEVEL[4:0] 24 H Reference level for Received Signal Strength Indication (carrier sense level) and AGC.

See Figure 5-15 for an explanation of the relationship between RSSI, AGC and carrier sense settings.

Table 5-39 LOCK Register (15h)(1)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
LOCK[7:4] LOCK_SELECT[3:0] 0 — Selection of signals to LOCK pin

0: Set to 0
1: Set to 1
2: LOCK_CONTINUOUS (active low)
3: LOCK_INSTANT (active low)
4: CARRIER_SENSE (RSSI above threshold, active low)
5: CAL_COMPLETE (active low)
6: SEQ_ERROR (active low)
7: FXOSC
8: REF_CLK
9: FILTER_CLK
10: DEC_CLK
11: PRE_CLK
12: DS_CLK
13: MODEM_CLK
14: VCO_CAL_COMP
15: F_COMP
LOCK[3] WINDOW_WIDTH 0 — Selects lock window width

0: Lock window is 2 prescaler clock cycles wide
1: Lock window is 4 prescaler clock cycles wide

Recommended setting: WINDOW_WIDTH=0.
LOCK[2] LOCK_MODE 0 — Selects lock detector mode

0: Counter restart mode
1: Up/Down counter mode

Recommended setting: LOCK_MODE=0.
LOCK[1:0] LOCK_ACCURACY[1:0] 0 — Selects lock accuracy (counter threshold values)

0: Declare lock at counter value 127, out of lock at value 111
1: Declare lock at counter value 255, out of lock at value 239
2: Declare lock at counter value 511, out of lock at value 495
3: Declare lock at counter value 1023, out of lock at value 1007
(1) Set LOCK_SELECT=2 to use the LOCK pin as a lock indicator.

Table 5-40 FRONTEND Register (16h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
FRONTEND[7:6] LNAMIX_CURRENT[1:0] 2 — Controls current in LNA, LNA2 and mixer

Recommended setting: LNAMIX_CURRENT=1
FRONTEND[5:4] LNA_CURRENT[1:0] 1 — Controls current in the LNA

Recommended setting: LNA_CURRENT=3.

Can be lowered to save power at the expense of reduced sensitivity.
FRONTEND[3] MIX_CURRENT 0 — Controls current in the mixer

Recommended setting:

MIX_CURRENT=1 at 426 to 464 MHz,
MIX_CURRENT=0 at 852 to 928 MHz.
FRONTEND[2] LNA2_CURRENT 0 — Controls current in LNA 2

Recommended settings:

LNA2_CURRENT=0 at 426 to 464 MHz,
LNA2_CURRENT=1 at 852 to 928 MHz.
FRONTEND[1] SDC_CURRENT 0 — Controls current in the single-to-diff. Converter

Recommended settings:

SDC_CURRENT=0 at 426 to 464 MHz,
SDC_CURRENT=1 at 852 to 928 MHz.
FRONTEND[0] LNAMIX_BIAS 1 — Controls how front-end bias currents are generated

0: Constant current biasing
1: Constant Gm × R biasing (reduces gain variation)

Recommended setting: LNAMIX_BIAS=0.

Table 5-41 ANALOG Register (17h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
ANALOG[7] BANDSELECT 1 — Frequency band selection

0: 402 to 470 MHz band
1: 804 to 930 MHz band
ANALOG[6] LO_DC 1 — Lower LO DC level to mixers

0: High LO DC level to mixers
1: Low LO DC level to mixers

Recommended settings:

LO_DC=1 for 402 to 470 MHz,
LO_DC=0 for 804 to 930 MHz.
ANALOG[5] VGA_BLANKING 1 H Enable analog blanking switches in VGA when changing VGA gain.

0: Blanking switches are disabled
1: Blanking switches are turned on for approx. 0.8 μs when gain is changed (always on if AGC_DISABLE=1)

Recommended setting: VGA_BLANKING=0.
ANALOG[4] PD_LONG 0 H Selects short or long reset delay in phase detector

0: Short reset delay
1: Long reset delay

Recommended setting: PD_LONG=0.
ANALOG[3] — 0 — Reserved, write 0
ANALOG[2] PA_BOOST 0 H Boost PA bias current for higher output power

Recommended setting: PA_BOOST=1.
ANALOG[1:0] DIV_BUFF_CURRENT[1:0] 3 — Overall bias current adjustment for VCO divider and buffers

0: 4/6 of nominal VCO divider and buffer current
1: 4/5 of nominal VCO divider and buffer current
2: Nominal VCO divider and buffer current
3: 4/3 of nominal VCO divider and buffer current

Recommended setting: DIV_BUFF_CURRENT=3

Table 5-42 BUFF_SWING Register (18h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
BUFF_SWING[7:6] PRE_SWING[1:0] 3 — Prescaler swing.

0: 2/3 of nominal swing
1: 1/2 of nominal swing
2: 4/3 of nominal swing
3: Nominal swing

Recommended setting: PRE_SWING=0.
BUFF_SWING[5:3] RX_SWING[2:0] 4 — LO buffer swing, in RX (to mixers)

0: Smallest load resistance (smallest swing)
…
7: Largest load resistance (largest swing)

Recommended setting: RX_SWING=2.
BUFF_SWING[2:0] TX_SWING[2:0] 1 — LO buffer swing, in TX (to power amplifier driver)

0: Smallest load resistance (smallest swing)
…
7: Largest load resistance (largest swing)

Recommended settings:

TX_SWING=4 for 402 to 470 MHz,
TX_SWING=0 for 804 to 930 MHz.

Table 5-43 BUFF_CURRENT Register (19h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
BUFF_CURRENT[7:6] PRE_CURRENT[1:0] 1 — Prescaler current scaling

0: Nominal current
1: 2/3 of nominal current
2: 1/2 of nominal current
3: 2/5 of nominal current

Recommended setting: PRE_CURRENT=0.
BUFF_CURRENT[5:3] RX_CURRENT[2:0] 4 — LO buffer current, in RX (to mixers)

0: Minimum buffer current
…
7: Maximum buffer current

Recommended setting: RX_CURRENT=4.
BUFF_CURRENT[2:0] TX_CURRENT[2:0] 5 — LO buffer current, in TX (to PA driver)

0: Minimum buffer current
…
7: Maximum buffer current

Recommended settings:

TX_CURRENT=2 for 402 to 470 MHz,
TX_CURRENT=5 for 804 to 930 MHz.

Table 5-44 PLL_BW Register (1Ah)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
PLL_BW[7:0] PLL_BW[7:0] 134 — Charge pump current scaling/rounding factor. Used to calibrate charge pump current for the desired PLL loop bandwidth.
The value is given by:
PLL_BW = 174 + 16 log2(fref / 7.126)
where fref is the reference frequency in MHz.

Table 5-45 CALIBRATE Register (1Bh)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
CALIBRATE[7] CAL_START 0 ↑ ↑ 1: Calibration started

0: Calibration inactive
CALIBRATE[6] CAL_DUAL 0 H Use calibration results for both frequency A and B

0: Store results in A or B defined by F_REG (MAIN[6])
1: Store calibration results in both A and B
CALIBRATE[5:4] CAL_WAIT[1:0] 0 — Selects calibration wait time (affects accuracy)

0 (00): Calibration time is approx. 90000 F_REF periods
1 (01): Calibration time is approx. 110000 F_REF periods
2 (10): Calibration time is approx. 130000 F_REF periods
3 (11): Calibration time is approx. 200000 F_REF periods

Recommended setting: CAL_WAIT=3 for best accuracy in calibrated PLL loop filter bandwidth.
CALIBRATE[3] — 0 — Reserved, write 0
CALIBRATE[2:0] CAL_ITERATE[2:0] 5 — Iteration start value for calibration DAC

0 (000): DAC start value 1, VC < 0.49 V after calibration
1 (001): DAC start value 2, VC < 0.66 V after calibration
2 (010): DAC start value 3, VC < 0.82 V after calibration
3 (011): DAC start value 4, VC < 0.99 V after calibration
4 (100): DAC start value 5, VC < 1.15 V after calibration
5 (101): DAC start value 6, VC < 1.32 V after calibration
6 (110): DAC start value 7, VC < 1.48 V after calibration
7 (111): DAC start value 8, VC < 1.65 V after calibration

Recommended setting: CAL_ITERATE=4.

Table 5-46 PA_POWER Register (1Ch)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
PA_POWER[7:4] PA_HIGH [3:0] 0 — Controls output power in high-power array

0: High-power array is off
1: Minimum high-power array output power
…
15: Maximum high-power array output power
PA_POWER[3:0] PA_LOW[3:0] 15 — Controls output power in low-power array

0: Low-power array is off
1: Minimum low-power array output power
…
15: Maximum low-power array output power

It is more efficient in terms of current consumption to use either the lower or upper 4-bits in the PA_POWER register to control the power.

Table 5-47 MATCH Register (1Dh)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
MATCH[7:4] RX_MATCH[3:0] 0 — Selects matching capacitor array value for RX. Each step is approximately 0.4 pF.
MATCH[3:0] TX_MATCH[3:0] 0 — Selects matching capacitor array value for TX.

Each step is approximately 0.4 pF.

Table 5-48 PHASE_COMP Register (1Eh)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
PHASE_COMP[7:0] PHASE_COMP[7:0] 0 — Signed compensation value for LO I/Q phase error. Used for image rejection calibration.

–128: approx. –6.2° adjustment between I and Q phase
–1: approx. –0.02° adjustment between I and Q phase
0: approx. +0.02° adjustment between I and Q phase
127: approx. +6.2° adjustment between I and Q phase

Table 5-49 GAIN_COMP Register (1Fh)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
GAIN_COMP[7:0] GAIN_COMP[7:0] 0 — Signed compensation value for mixer I/Q gain error. Used for image rejection calibration.

–128: approx. –1.16 dB adjustment between I and Q gain
–1: approx. –0.004 dB adjustment between I and Q gain
0: approx. +0.004 dB adjustment between I and Q gain
127: approx. +1.16 dB adjustment between I and Q gain

Table 5-50 POWERDOWN Register (20h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
POWERDOWN[7] PA_PD 0 H Sets PA in power down when PD_MODE[1:0]=2
POWERDOWN[6] VCO_PD 0 H Sets VCO in power down when PD_MODE[1:0]=2
POWERDOWN[5] BUFF_PD 0 H Sets VCO divider, LO buffers and prescaler in power-down when PD_MODE[1:0]=2
POWERDOWN[4] CHP_PD 0 H Sets charge pump in power down when PD_MODE[1:0]=2
POWERDOWN[3] LNAMIX_PD 0 H Sets LNA/mixer in power down when PD_MODE[1:0]=2
POWERDOWN[2] VGA_PD 0 H Sets VGA in power down when PD_MODE[1:0]=2
POWERDOWN[1] FILTER_PD 0 H Sets image filter in power down when PD_MODE[1:0]=2
POWERDOWN[0] ADC_PD 0 H Sets ADC in power down when PD_MODE[1:0]=2

Table 5-51 TEST1 Register (21h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
TEST1[7:4] CAL_DAC_OPEN[3:0] 4 — Calibration DAC override value, active when BREAK_LOOP=1
TEST1[3:0] CHP_CO[3:0] 13 — Charge pump current override value

Table 5-52 TEST2 Register (22h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
TEST2[7] BREAK_LOOP 0 H 0: PLL loop closed
1: PLL loop open
TEST2[6] CHP_OVERRIDE 0 H 0: use calibrated value
1: use CHP_CO[3:0] value
TEST2[5] VCO_OVERRIDE 0 H 0: use calibrated value
1: use VCO_AO[4:0] value
TEST2[4:0] VCO_AO[4:0] 16 — VCO_ARRAY override value

Table 5-53 TEST3 Register (23h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
TEST3[7] VCO_CAL_MANUAL 0 H Enables “manual” VCO calibration (test only)
TEST3[6] VCO_CAL_OVERRIDE 0 H Override VCO current calibration

0: Use calibrated value
1: Use VCO_CO[5:0] value

VCO_CAL_OVERRIDE controls VCO_CAL_CLK
if VCO_CAL_MANUAL=1. Negative transitions are then used to sample VCO_CAL_COMP.
TEST3[5:0] VCO_CO[5:0] 6 — VCO_CAL_CURRENT override value

Table 5-54 TEST4 Register (24h, for Test Only)(1)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
TEST4[7] CHP_DISABLE 0 H Disable normal charge pump operation
TEST4[6] CHP_TEST_UP 0 H Force charge pump to output “up” current
TEST4[5] CHP_TEST_DN 0 H Force charge pump to output “down” current
TEST4[4:3] TM_IQ[1:0] 0 — Value of differential I and Q outputs from mixer when TM_ENABLE=1

0: I output negative, Q output negative
1: I output negative, Q output positive
2: I output positive, Q output negative
3: I output positive, Q output positive
TEST4[2] TM_ENABLE 0 H Enable DC control of mixer output (for testing)
TEST4[1] TF_ENABLE 0 H Connect analog test module to filter inputs
TEST4[0] TA_ENABLE 0 H Connect analog test module to ADC inputs
(1) If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2]=1.

Table 5-55 TEST5 Register (25h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
TEST5[7] F_COMP_ENABLE 0 H Enable frequency comparator output F_COMP from phase detector
TEST5[6] SET_DITHER_CLOCK 1 H Enable dithering of delta-sigma clock
TEST5[5] ADC_TEST_OUT 0 H Outputs ADC samples on LOCK and DIO, while ADC_CLK is output on DCLK
TEST5[4] CHOP_DISABLE 0 H Disable chopping in ADC integrators
TEST5[3] SHAPING_DISABLE 0 H Disable ADC feedback mismatch shaping
TEST5[2] VCM_ROT_DISABLE 0 H Disable rotation for VCM mismatch shaping
TEST5[1:0] ADC_ROTATE[1:0] 0 — Control ADC input rotation

0: Rotate in 00 01 10 11 sequence
1: Rotate in 00 10 11 01 sequence
2: Always use 00 position
3: Rotate in 00 10 00 10 sequence

Table 5-56 TEST6 Register (26h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
TEST6[7:4] — 0 — Reserved, write 0
TEST6[3] VGA_OVERRIDE 0 — Override VGA settings
TEST6[2] AC1O 0 — Override value to first AC coupler in VGA

0: Approx. 0 dB gain
1: Approx. –12 dB gain
TEST6[1:0] AC2O[1:0] 0 — Override value to second AC coupler in VGA

0: Approx. 0 dB gain
1: Approx. –3 dB gain
2: Approx. –12 dB gain
3: Approx. –15 dB gain

Table 5-57 TEST7 Register (27h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
TEST7[7:6] — 0 — Reserved, write 0
TEST7[5:4] VGA1O[1:0] 0 — Override value to VGA stage 1
TEST7[3:2] VGA2O[1:0] 0 — Override value to VGA stage 2
TEST7[1:0] VGA3O[1:0] 0 — Override value to VGA stage 3

Table 5-58 STATUS Register (40h, Read Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS[7] CAL_COMPLETE — H Set to 0 when PLL calibration starts, and set to 1 when calibration has finished
STATUS[6] SEQ_ERROR — H Set to 1 when PLL failed to lock during automatic power-up sequencing
STATUS[5] LOCK_INSTANT — H Instantaneous PLL lock indicator
STATUS[4] LOCK_CONTINUOUS — H

PLL lock indicator, as defined by LOCK_ACCURACY.

Set to 1 when PLL is in lock
STATUS[3] CARRIER_SENSE — H Carrier sense when RSSI is above CS_LEVEL
STATUS[2] LOCK — H Logical level on LOCK pin
STATUS[1] DCLK — H Logical level on DCLK pin
STATUS[0] DIO — H Logical level on DIO pin

Table 5-59 RESET_DONE Register (41h, Read Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
RESET_DONE[7] ADC_RESET_DONE — H Reset of ADC control logic done
RESET_DONE[6] AGC_RESET_DONE — H Reset of AGC (VGA control) logic done
RESET_DONE[5] GAUSS_RESET_DONE — H Reset of Gaussian data filter done
RESET_DONE[4] AFC_RESET_DONE — H Reset of AFC / FSK decision level logic done
RESET_DONE[3] BITSYNC_RESET_DONE — H Reset of modulator, bit synchronization logic and PN9 PRBS generator done
RESET_DONE[2] SYNTH_RESET_DONE — H Reset digital part of frequency synthesizer done
RESET_DONE[1] SEQ_RESET_DONE — H Reset of power-up sequencing logic done
RESET_DONE[0] CAL_LOCK_RESET_DONE — H Reset of calibration logic and lock detector done

Table 5-60 RSSI Register (42h, Read Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
RSSI[7] — — — Not in use, will read 0
RSSI[6:0] RSSI[6:0] — — Received signal strength indicator.

The relative power is given by RSSI × 1.5 dB in a logarithmic scale.

The VGA gain set by VGA_SETTING must be taken into account. See Section 5.9.5 for more details.

Table 5-61 AFC Register (43h, Read Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
AFC[7 :0] AFC[7:0] — — Average received frequency deviation from IF. This 8-bit 2-complement signed value equals the demodulator decision level and can be used for AFC.
The average frequency offset from the IF frequency is
ΔF = Baud rate × AFC / 16

Table 5-62 GAUSS_FILTER Register (44h)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
GAUSS_FILTER[7 :0] GAUSS_FILTER[7:0] — — Readout of instantaneous IF frequency offset from nominal IF. Signed 8-bit value.
ΔF = Baud rate × GAUSS_FILTER / 8

Table 5-63 STATUS1 Register (45h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS1[7:4] CAL_DAC[3:0] — — Status vector defining applied Calibration DAC value
STATUS1[3:0] CHP_CURRENT[3:0] — — Status vector defining applied CHP_CURRENT value

Table 5-64 STATUS2 Register (46h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS2[7:5] CC1020_VERSION[2:0] — — CC1020 device version code:

0 : Pre-production version
1: First production version
2 through 7: Reserved for future use
STATUS2[4:0] VCO_ARRAY[4:0] — — Status vector defining applied VCO_ARRAY value

Table 5-65 STATUS3 Register (47h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS3[7] F_COMP — — Frequency comparator output from phase detector
STATUS3[6] VCO_CAL_COMP — — Readout of VCO current calibration comparator.

Equals 1 if current defined by VCO_CURRENT_A/B is larger than the VCO core current
STATUS3[5:0] VCO_CAL_CURRENT[5:0] — — Status vector defining applied VCO_CAL_CURRENT value

Table 5-66 STATUS4 Register (48h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS4[7:6] ADC_MIX[1:0] — — Readout of mixer input to ADC
STATUS4[5:3] ADC_I[2:0] — — Readout of ADC “I” output
STATUS4[2:0] ADC_Q[2:0] — — Readout of ADC “Q” output

Table 5-67 STATUS5 Register (49h, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS5[7:0] FILTER_I[7:0] — — Upper bits of “I” output from channel filter

Table 5-68 STATUS6 Register (4Ah, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS6[7:0] FILTER_Q[7:0] — — Upper bits of “Q” output from channel filter

Table 5-69 STATUS7 Register (4Bh, for Test Only)

REGISTER NAME DEFAULT VALUE ACTIVE DESCRIPTION
STATUS7[7:5] — — — Not in use, will read 0
STATUS7[4:0] VGA_GAIN_OFFSET[4:0] — — Readout of offset between VGA_SETTING and actual VGA gain set by AGC