The CC110L is a cost optimized sub-1 GHz RF transceiver for the 300–348 MHz, 387–464 MHz, and 779–928 MHz frequency bands. The circuit is based on the popular CC1101 RF transceiver, and RF performance characteristics are identical. Two CC110L transceivers together enable a low-cost bidirectional RF link.
The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 600 kbps.
The CC110L provides extensive hardware support for packet handling, data buffering, and burst transmissions.
The main operating parameters and the 64-byte receive and transmit FIFOs of CC110L can be controlled through a serial peripheral interface (SPI). In a typical system, the CC110L will be used together with a microcontroller and a few additional passive components.
Figure 1-1 shows a functional block diagram of the device.
Changes from B Revision (June 2014) to C Revision
The CC110L pinout is shown in Figure 3-1 and Table 3-1. See Section 5.25 for details on the I/O configuration.
Pin No. | Pin Name | Pin Type | Description |
---|---|---|---|
1 | SCLK | Digital Input | Serial configuration interface, clock input |
2 | SO (GDO1) | Digital Output | Serial configuration interface, data output |
Optional general output pin when CSn is high | |||
3 | GDO2 | Digital Output | Digital output pin for general use:
|
4 | DVDD | Power (Digital) | 1.8 - 3.6 V digital power supply for digital I/O's and for the digital core voltage regulator |
5 | DCOUPL | Power (Digital) | 1.6 - 2.0 V digital power supply output for decoupling |
NOTE: This pin is intended for use with the CC110L only. It can not be used to provide supply voltage to other devices |
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6 | GDO0 | Digital I/O | Digital output pin for general use:
|
7 | CSn | Digital Input | Serial configuration interface, chip select |
8 | XOSC_Q1 | Analog I/O | Crystal oscillator pin 1, or external clock input |
9 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection |
10 | XOSC_Q2 | Analog I/O | Crystal oscillator pin 2 |
11 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection |
12 | RF_P | RF I/O | Positive RF input signal to LNA in receive mode |
Positive RF output signal from PA in transmit mode | |||
13 | RF_N | RF I/O | Negative RF input signal to LNA in receive mode |
Negative RF output signal from PA in transmit mode | |||
14 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection |
15 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection |
16 | GND | Ground (Analog) | Analog ground connection |
17 | RBIAS | Analog I/O | External bias resistor for reference current |
18 | DGUARD | Power (Digital) | Power supply connection for digital noise isolation |
19 | GND | Ground (Digital) | Ground connection for digital noise isolation |
20 | SI | Digital Input | Serial configuration interface, data input |
Parameter | Min | Max | Units | Condition |
---|---|---|---|---|
Supply voltage | –0.3 | 3.9 | V | All supply pins must have the same voltage |
Voltage on any digital pin | –0.3 | VDD + 0.3, max 3.9 | V | |
Voltage on the pins RF_P, RF_N, DCOUPL, RBIAS | –0.3 | 2.0 | V | |
Voltage ramp-up rate | 120 | kV/µs | ||
Input RF level | +10 | dBm |
Parameter | MIN | MAX | UNIT | |
---|---|---|---|---|
Storage temperature range, Tstg | (default) | –50 | 150 | °C |
ESD Stress Voltage, VESD | Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) | 750 | V | |
Charged Device Model (CDM), per JJESD22-C101(2) | 400 | V |
Parameter | Min | Max | Unit | Condition |
---|---|---|---|---|
Operating temperature | –40 | 85 | °C | |
Operating supply voltage | 1.8 | 3.6 | V | All supply pins must have the same voltage |
Parameter | Min | Typ | Max | Unit | Condition |
---|---|---|---|---|---|
Frequency range | 300 | 348 | MHz | ||
387 | 464 | MHz | If using a 27 MHz crystal, the lower frequency limit for this band is 392 MHz | ||
779 | 928 | MHz | |||
Data rate | 0.6 | 500 | kBaud | 2-FSK | |
0.6 | 250 | kBaud | GFSK and OOK | ||
0.6 | 300 | kBaud | 4-FSK (the data rate in kbps will be twice the baud rate) Optional Manchester encoding (the data rate in kbps will be half the baud rate) |
TA = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using SWRR046 and SWRR045. Reduced current settings, MDMCFG2.DEM_DCFILT_OFF=1, gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Section 4.7 for additional details on current consumption and sensitivity.
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Parameter | Min | Typ | Max | Unit | Condition |
---|---|---|---|---|---|
Current consumption in power down modes | 0.2 | 1 | µA | Voltage regulator to digital part off, register values retained (SLEEP state). All GDO pins programmed to 0x2F (HW to 0) | |
100 | µA | Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set) | |||
165 | µA | Voltage regulator to digital part on, all other modules in power down (XOFF state) | |||
Current consumption | 1.7 | mA | Only voltage regulator to digital part and crystal oscillator running (IDLE state) | ||
8.4 | mA | Only the frequency synthesizer is running (FSTXON state). This currents consumption is also representative for the other intermediate states when going from IDLE to RX or TX, including the calibration state | |||
Current consumption, 315 MHz | 15.4 | mA | Receive mode, 1.2 kBaud, reduced current, input at sensitivity limit | ||
14.4 | mA | Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit | |||
15.2 | mA | Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit | |||
14.3 | mA | Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit | |||
16.5 | mA | Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit | |||
15.1 | mA | Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit | |||
27.4 | mA | Transmit mode, +10 dBm output power | |||
15.0 | mA | Transmit mode, 0 dBm output power | |||
12.3 | mA | Transmit mode, –6 dBm output power | |||
Current consumption, 433 MHz | 16.0 | mA | Receive mode, 1.2 kBaud, register settings optimized for reduced current, input at sensitivity limit | ||
15.0 | mA | Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit | |||
15.7 | mA | Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit | |||
15.0 | mA | Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit | |||
17.1 | mA | Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit | |||
15.7 | mA | Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit | |||
29.2 | mA | Transmit mode, +10 dBm output power | |||
16.0 | mA | Transmit mode, 0 dBm output power | |||
13.1 | mA | Transmit mode, –6 dBm output power | |||
Current consumption, 868/915 MHz | 15.7 | mA | Receive mode, 1.2 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 4-1 through Figure 4-3 for current consumption with register settings optimized for sensitivity. |
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14.7 | mA | Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 4-1 through Figure 4-3 for current consumption with register settings optimized for sensitivity. |
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15.6 | mA | Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 4-1 through Figure 4-3 for current consumption with register settings optimized for sensitivity. |
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14.6 | mA | Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 4-1 through Figure 4-3 for current consumption with register settings optimized for sensitivity. |
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16.9 | mA | Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 4-1 through Figure 4-3 for current consumption with register settings optimized for sensitivity. |
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15.6 | mA | Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 4-1 through Figure 4-3 for current consumption with register settings optimized for sensitivity. |
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34.2 | mA | Transmit mode, +12 dBm output power, 868 MHz | |||
30.0 | mA | Transmit mode, +10 dBm output power, 868 MHz | |||
16.8 | mA | Transmit mode, 0 dBm output power, 868 MHz | |||
16.4 | mA | Transmit mode, –6 dBm output power, 868 MHz. | |||
33.4 | mA | Transmit mode, +11 dBm output power, 915 MHz | |||
30.7 | mA | Transmit mode, +10 dBm output power, 915 MHz | |||
17.2 | mA | Transmit mode, 0 dBm output power, 915 MHz | |||
17.0 | mA | Transmit mode, –6 dBm output power, 915 MHz |
Supply Voltage | Supply Voltage | Supply Voltage | |||||||
---|---|---|---|---|---|---|---|---|---|
VDD = 1.8 V | VDD = 3.0 V | VDD = 3.6 V | |||||||
Temperature [°C] | −40 | 25 | 85 | −40 | 25 | 85 | −40 | 25 | 85 |
Current [mA], PATABLE=0xC0, +12 dBm | 32.7 | 31.5 | 30.5 | 35.3 | 34.2 | 33.3 | 35.5 | 34.4 | 33.5 |
Current [mA], PATABLE=0xC5, +10 dBm | 30.1 | 29.2 | 28.3 | 30.9 | 30.0 | 29.4 | 31.1 | 30.3 | 29.6 |
Current [mA], PATABLE=0x50, 0 dBm | 16.4 | 16.0 | 15.6 | 17.3 | 16.8 | 16.4 | 17.6 | 17.1 | 16.7 |
Supply Voltage | Supply Voltage | Supply Voltage | |||||||
---|---|---|---|---|---|---|---|---|---|
VDD = 1.8 V | VDD = 3.0 V | VDD = 3.6 V | |||||||
Temperature [°C] | −40 | 25 | 85 | −40 | 25 | 85 | −40 | 25 | 85 |
Current [mA], PATABLE=0xC0, +11 dBm | 31.9 | 30.7 | 29.8 | 34.6 | 33.4 | 32.5 | 34.8 | 33.6 | 32.7 |
Current [mA], PATABLE=0xC3, +10 dBm | 30.9 | 29.8 | 28.9 | 31.7 | 30.7 | 30.0 | 31.9 | 31.0 | 30.2 |
Current [mA], PATABLE=0x8E, 0 dBm | 17.2 | 16.8 | 16.4 | 17.6 | 17.2 | 16.9 | 17.8 | 17.4 | 17.1 |
See Section 4.14.1.
Parameter | Min | Typ | Max | Unit | Condition |
---|---|---|---|---|---|
Digital channel filter bandwidth | 58 | 812 | kHz | User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal) | |
Spurious emissions | –68 | –57 | dBm | 25 MHz - 1 GHz | |
(Maximum figure is the ETSI EN 300 220 V2.3.1 limit) | |||||
–66 | –47 | dBm | Above 1 GHz | ||
(Maximum figure is the ETSI EN 300 220 V2.3.1 limit) | |||||
Typical radiated spurious emission is –49 dBm measured at the VCO frequency | |||||
RX latency | 9 | bit | Serial operation. Time from start of reception until data is available on the receiver data output pin is equal to 9 bit | ||
315 MHz | |||||
1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –111 | dBm | Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.2 mA to 15.4 mA at the sensitivity limit. The sensitivity is typically reduced to -109 dBm | ||
433 MHz | |||||
0.6 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(GFSK, 1% packet error rate, 20 bytes packet length, 14.3 kHz deviation, 58 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –116 | dBm | |||
1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –112 | dBm | Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.0 mA to 16.0 mA at the sensitivity limit. The sensitivity is typically reduced to –110 dBm | ||
38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –104 | dBm | |||
250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –95 | dBm | |||
868/915 MHz | |||||
1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –112 | dBm | Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.7 mA at sensitivity limit. The sensitivity is typically reduced to –109 dBm | ||
Saturation | –14 | dBm | FIFOTHR.CLOSE_IN_RX=0. See more in DN010 SWRA147 | ||
Adjacent channel rejection ±100 kHz offset | 37 | dB | Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing See Figure 4-4 and Figure 4-5 for selectivity performance at other offset frequencies |
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Image channel rejection | 31 | dB | IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit |
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Blocking | Desired channel 3 dB above the sensitivity limit See Figure 4-4 and Figure 4-5 for blocking performance at other offset frequencies |
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±2 MHz offset | –50 | dBm | |||
±10 MHz offset | –40 | dBm | |||
38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –104 | dBm | Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.6 mA at the sensitivity limit. The sensitivity is typically reduced to -102 dBm | ||
Saturation | –16 | dBm | FIFOTHR.CLOSE_IN_RX=0. See more in DN010 SWRA147 | ||
Adjacent channel rejection | Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing See Figure 4-6 and Figure 4-7 for blocking performance at other offset frequencies |
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–200 kHz offset | 12 | dB | |||
+200 kHz offset | 25 | dB | |||
Image channel rejection | 23 | dB | IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit |
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Blocking | Desired channel 3 dB above the sensitivity limit See Figure 4-6 and Figure 4-7 for blocking performance at other offset frequencies |
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±2 MHz offset | –50 | dBm | |||
±10 MHz offset | –40 | dBm | |||
250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | |||||
(GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) | |||||
Receiver sensitivity | –95 | dBm | Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.9 mA to 16.9 mA at the sensitivity limit. The sensitivity is typically reduced to -91 dBm | ||
Saturation | –17 | dBm | FIFOTHR.CLOSE_IN_RX=0. See more in DN010 SWRA147 | ||
Adjacent channel rejection | 25 | dB | Desired channel 3 dB above the sensitivity limit. 750-kHz channel spacing See Figure 4-8 and Figure 4-9 for blocking performance at other offset frequencies |
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Image channel rejection | 14 | dB | IF frequency 304 kHz Desired channel 3 dB above the sensitivity limit |
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Blocking | Desired channel 3 dB above the sensitivity limit See Figure 4-8 and Figure 4-9 for blocking performance at other offset frequencies |
Supply Voltage | Supply Voltage | Supply Voltage | |||||||
---|---|---|---|---|---|---|---|---|---|
VDD = 1.8 V | VDD = 3.0 V | VDD = 3.6 V | |||||||
Temperature [°C] | –40 | 25 | 85 | –40 | 25 | 85 | –40 | 25 | 85 |
Sensitivity [dBm] 1.2 kBaud | –113 | –112 | –110 | –113 | –112 | –110 | –113 | –112 | –110 |
Sensitivity [dBm] 38.4 kBaud | –105 | –104 | –102 | –105 | –104 | –102 | –105 | –104 | –102 |
Sensitivity [dBm] 250 kBaud | –97 | –96 | –92 | –97 | –95 | –92 | –97 | –94 | –92 |
Supply Voltage | Supply Voltage | Supply Voltage | |||||||
---|---|---|---|---|---|---|---|---|---|
VDD = 1.8 V | VDD = 3.0 V | VDD = 3.6 V | |||||||
Temperature [°C] | –40 | 25 | 85 | –40 | 25 | 85 | –40 | 25 | 85 |
Sensitivity [dBm] 1.2 kBaud | –113 | –112 | –110 | –113 | –112 | –110 | –113 | –112 | –110 |
Sensitivity [dBm] 38.4 kBaud | –105 | –104 | –102 | –104 | –104 | –102 | –105 | –104 | –102 |
Sensitivity [dBm] 250 kBaud | –97 | –94 | –92 | –97 | –95 | –92 | –97 | –95 | –92 |
See Section 4.14.2.
Parameter | Min | Typ | Max | Unit | Condition |
---|---|---|---|---|---|
Differential load impedance | Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. | ||||
315 MHz | 122 + j31 | Ω | |||
433 MHz | 116 + j41 | Ω | |||
868/915 MHz | 86.5 + j43 | Ω | |||
Output power, highest setting | Output power is programmable, and full range is available in all frequency bands. Output power may be restricted by regulatory limits. See Design Note DN013 SWRA168 for output power and harmonics figures when using multi-layer inductors. The output power is then typically +10 dBm when operating at 868/915 MHz. Delivered to a 50-Ω single-ended load through the RF matching network in SWRR046 and SWRR045 |
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315 MHz | +10 | dBm | |||
433 MHz | +10 | dBm | |||
868 MHz | +12 | dBm | |||
915 MHz | +11 | dBm | |||
Output power, lowest setting | −30 | dBm | Output power is programmable, and full range is available in all frequency bands Delivered to a 50-Ω single-ended load through the RF matching network in SWRR046 and SWRR045 |
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Harmonics, radiated | Measured on SWRR046 and SWRR045 with CW, maximum output power The antennas used during the radiated measurements (SMAFF-433 from R.W. Badland and Nearson S331 868/915) play a part in attenuating the harmonics Note: All harmonics are below −41.2 dBm when operating in the 902 - 928 MHz band |
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2nd Harm, 433 MHz | −49 | dBm | |||
3rd Harm, 433 MHz | −40 | dBm | |||
2nd Harm, 868 MHz | −47 | dBm | |||
3rd Harm, 868 MHz | −55 | dBm | |||
2nd Harm, 915 MHz | −50 | dBm | |||
3rd Harm, 915 MHz | −54 | dBm | |||
Harmonics, conducted | Measured with +10 dBm CW at 315 MHz and 433 MHz | ||||
315 MHz | < −35 | dBm | Frequencies below 960 MHz | ||
< −53 | dBm | Frequencies above 960 MHz | |||
433 MHz | −43 | dBm | Frequencies below 1 GHz | ||
< −45 | dBm | Frequencies above 1 GHz | |||
868 MHz 2nd Harm other harmonics | −36 | dBm | Measured with +12 dBm CW at 868 MHz | ||
< −46 | dBm | ||||
915 MHz 2nd Harm other harmonics | −34 | dBm | Measured with +11 dBm CW at 915 MHz (requirement is −20 dBc under FCC 15.247) | ||
< −50 | dBm | ||||
Spurious emissions conducted, harmonics not included | Measured with +10 dBm CW at 315 MHz and 433 MHz | ||||
315 MHz | < −58 | Frequencies below 960 MHz | |||
< −53 | Frequencies above 960 MHz | ||||
433 MHz | < −50 | Frequencies below 1 GHz | |||
< −54 | Frequencies above 1 GHz | ||||
< −56 | Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz | ||||
Measured with +12 dBm CW at 868 MHz | |||||
868 MHz | < −50 | Frequencies below 1 GHz | |||
< −52 | Frequencies above 1 GHz | ||||
< −53 | Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz | ||||
All radiated spurious emissions are within the limits of ETSI. The peak conducted spurious emission is −53 dBm at 699 MHz (868 MHz - 169 MHz), which is in a frequency band limited to −54 dBm by EN 300 220 V2.3.1. An alternative filter can be used to reduce the emission at 699 MHz below −54 dBm, for conducted measurements, and is shown in Figure 6-2. See more information in DN017 SWRA168. | |||||
For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz. | |||||
Measured with +11 dBm CW at 915 MHz | |||||
915 MHz | < −51 | Frequencies below 960 MHz | |||
< −54 | Frequencies above 960 MHz | ||||
TX latency | 8 | bit | Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports |
Supply Voltage | Supply Voltage | Supply Voltage | |||||||
---|---|---|---|---|---|---|---|---|---|
VDD = 1.8 V | VDD = 3.0 V | VDD = 3.6 V | |||||||
Temperature [°C] | −40 | 25 | 85 | −40 | 25 | 85 | −40 | 25 | 85 |
Output Power [dBm], PATABLE=0xC0, +12 dBm | 12 | 11 | 10 | 12 | 12 | 11 | 12 | 12 | 11 |
Output Power [dBm], PATABLE=0xC5, +10 dBm | 11 | 10 | 9 | 11 | 10 | 10 | 11 | 10 | 10 |
Output Power [dBm], PATABLE=0x50, 0 dBm | 1 | 0 | -1 | 2 | 1 | 0 | 2 | 1 | 0 |
Supply Voltage | Supply Voltage | Supply Voltage | |||||||
---|---|---|---|---|---|---|---|---|---|
VDD = 1.8 V | VDD = 3.0 V | VDD = 3.6 V | |||||||
Temperature [°C] | −40 | 25 | 85 | −40 | 25 | 85 | −40 | 25 | 85 |
Output Power [dBm], PATABLE=0xC0, +11 dBm | 11 | 10 | 10 | 12 | 11 | 11 | 12 | 11 | 11 |
Output Power [dBm], PATABLE=0x8E, +0 dBm | 2 | 1 | 0 | 2 | 1 | 0 | 2 | 1 | 0 |
Parameter | Min | Typ | Max | Unit | Condition |
---|---|---|---|---|---|
Crystal frequency | 26 | 26 | 27 | MHz | For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz. |
Tolerance | ±40 | ppm | This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. | ||
Load capacitance | 10 | 13 | 20 | pF | Simulated over operating conditions |
ESR | 100 | Ω | |||
Start-up time | 150 | µs | This parameter is to a large degree crystal dependent. Measured on SWRR046 and SWRR045 using crystal AT-41CD2 from NDK |
Parameter | Min | Typ | Max | Unit | Condition |
---|---|---|---|---|---|
Programmed frequency resolution | 397 | FXOSC/216 | 412 | Hz | 26- to 27-MHz crystal. The resolution (in Hz) is equal for all frequency bands |
Synthesizer frequency tolerance | ±40 | ppm | Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing | ||
RF carrier phase noise | –92 | dBc/Hz | at 50 kHz offset from carrier | ||
RF carrier phase noise | –92 | dBc/Hz | at 100 kHz offset from carrier | ||
RF carrier phase noise | –92 | dBc/Hz | at 200 kHz offset from carrier | ||
RF carrier phase noise | –98 | dBc/Hz | at 500 kHz offset from carrier | ||
RF carrier phase noise | –107 | dBc/Hz | at 1 MHz offset from carrier | ||
RF carrier phase noise | –113 | dBc/Hz | at 2 MHz offset from carrier | ||
RF carrier phase noise | –119 | dBc/Hz | at 5 MHz offset from carrier | ||
RF carrier phase noise | –129 | dBc/Hz | at 10 MHz offset from carrier | ||
PLL turn-on or hop time (See Table 5-11) |
72 | 75 | 75 | µs | Time from leaving the IDLE state until arriving in the RX, FSTXON, or TX state, when not performing calibration. Crystal oscillator running. |
PLL RX/TX settling time (See Table 5-11) |
29 | 30 | 30 | µs | Settling time for the 1×IF frequency step from RX to TX |
PLL TX/RX settling time (See Table 5-11) |
30 | 31 | 31 | µs | Settling time for the 1×IF frequency step from TX to RX. 250 kbps data rate. |
PLL calibration time (See Table 5-12) |
685 | 712 | 724 | µs | Calibration can be initiated manually or automatically before entering or after leaving RX/TX |
Digital Inputs/Outputs | Min | Max | Unit | Condition |
---|---|---|---|---|
Logic "0" input voltage | 0 | 0.7 | V | |
Logic "1" input voltage | VDD – 0.7 | VDD | V | |
Logic "0" output voltage | 0 | 0.5 | V | For up to 4 mA output current |
Logic "1" output voltage | VDD – 0.3 | VDD | V | For up to 4 mA output current |
Logic "0" input current | N/A | –50 | nA | Input equals 0 V |
Logic "1" input current | N/A | 50 | nA | Input equals VDD |
Parameter | Min | Typ | Max | Unit | Condition |
---|---|---|---|---|---|
Power-up ramp-up time | 5 | ms | From 0 V until reaching 1.8 V | ||
Power off time | 1 | ms | Minimum time between power-on and power-off |
NAME | DESCRIPTION | QFN (°C/W) |
---|---|---|
RθJA | Junction-to-ambient thermal resistance | 47 |
RθJC(top) | Junction-to-case (top) thermal resistance | 45 |
RθJB | Junction-to-board thermal resistance | 13.6 |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 5.12 |