SWRS111F June   2011  – October 2014 CC1121

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Configuration
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions (General Characteristics)
    4. 4.4  Thermal Resistance Characteristics for RHB Package
    5. 4.5  RF Characteristics
    6. 4.6  Regulatory Standards
    7. 4.7  Current Consumption, Static Modes
    8. 4.8  Current Consumption, Transmit Modes
      1. 4.8.1 950-MHz Band (High-Performance Mode)
      2. 4.8.2 868-, 915-, and 920-MHz Bands (High-Performance Mode)
      3. 4.8.3 434-MHz Band (High-Performance Mode)
      4. 4.8.4 169-MHz Band (High-Performance Mode)
      5. 4.8.5 Low-Power Mode
    9. 4.9  Current Consumption, Receive Modes
      1. 4.9.1 High-Performance Mode
      2. 4.9.2 Low-Power Mode
    10. 4.10 Receive Parameters
      1. 4.10.1 General Receive Parameters (High-Performance Mode)
      2. 4.10.2 RX Performance in 950-MHz Band (High-Performance Mode)
      3. 4.10.3 RX Performance in 868-, 915-, and 920-MHz Bands (High-Performance Mode)
      4. 4.10.4 RX Performance in 434-MHz Band (High-Performance Mode)
      5. 4.10.5 RX Performance in 169-MHz Band (High-Performance Mode)
      6. 4.10.6 RX Performance in Low-Power Mode
    11. 4.11 Transmit Parameters
    12. 4.12 PLL Parameters
      1. 4.12.1 High-Performance Mode
      2. 4.12.2 Low-Power Mode
    13. 4.13 Wake-up and Timing
    14. 4.14 32-MHz Crystal Oscillator
    15. 4.15 32-MHz Clock Input (TCXO) data to TCXO table
    16. 4.16 32-kHz Clock Input
    17. 4.17 32-kHz RC Oscillator
    18. 4.18 I/O and Reset
    19. 4.19 Temperature Sensor
    20. 4.20 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Block Diagram
    2. 5.2  Frequency Synthesizer
    3. 5.3  Receiver
    4. 5.4  Transmitter
    5. 5.5  Radio Control and User Interface
    6. 5.6  Enhanced Wake-On-Radio (eWOR)
    7. 5.7  Sniff Mode
    8. 5.8  Antenna Diversity
    9. 5.9  Low-Power and High-Performance Mode
    10. 5.10 WaveMatch
  6. 6Typical Application Circuit
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Configuration Software
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Terminal Configuration and Functions

3.1 Pin Diagram

Figure 3-1 shows pin names and locations for the CC1121 device.

po_swrs111.gifFigure 3-1 Package 5-mm × 5-mm QFN

3.2 Pin Configuration

The following table lists the pinout configuration for the CC1121 device.

PIN NO. PIN NAME TYPE / DIRECTION DESCRIPTION
1 VDD_GUARD Power 2.0–3.6 V VDD
2 RESET_N Digital input Asynchronous, active-low digital reset
3 GPIO3 Digital I/O General-purpose I/O
4 GPIO2 Digital I/O General-purpose I/O
5 DVDD Power 2.0–3.6 V VDD to internal digital regulator
6 DCPL Power Digital regulator output to external decoupling capacitor
7 SI Digital input Serial data in
8 SCLK Digital input Serial data clock
9 SO(GPIO1) Digital I/O Serial data out (general-purpose I/O)
10 GPIO0 Digital I/O General-purpose I/O
11 CSn Digital Input Active-low chip select
12 DVDD Power 2.0–3.6 V VDD
13 AVDD_IF Power 2.0–3.6 V VDD
14 RBIAS Analog External high-precision R
15 AVDD_RF Power 2.0–3.6 V VDD
16 N.C. Not connected
17 PA Analog Single-ended TX output (requires DC path to VDD)
18 TRX_SW Analog TX and RX switch. Connected internally to GND in TX and floating (high-impedance) in RX.
19 LNA_P Analog Differential RX input (requires DC path to GND)
20 LNA_N Analog Differential RX input (requires DC path to GND)
21 DCPL_VCO Power Pin for external decoupling of VCO supply regulator
22 AVDD_SYNTH1 Power 2.0–3.6 V VDD
23 LPF0 Analog External loop filter components
24 LPF1 External loop filter components
25 AVDD_PFD_CHP Power 2.0–3.6 V VDD
26 DCPL_PFD_CHP Power Pin for external decoupling of PFD and CHP regulator
27 AVDD_SYNTH2 Power 2.0–3.6 V VDD
28 AVDD_XOSC Power 2.0–3.6 V VDD
29 DCPL_XOSC Power Pin for external decoupling of XOSC supply regulator
30 XOSC_Q1 Analog Crystal oscillator pin 1 (must be grounded if a TCXO or other external clock connected to EXT_XOSC is used)
31 XOSC_Q2 Analog Crystal oscillator pin 2 (must be left floating if a TCXO or other external clock connected to EXT_XOSC is used)
32 EXT_XOSC Digital input Pin for external XOSC input (must be grounded if a regular XOSC connected to XOSC_Q1 and XOSC_Q2 is used)
– GND Ground pad The ground pad must be connected to a solid ground plane.