CC113L Value Line Receiver

1.1 Features

• RF Performance
• Receive Sensitivity Down to −116 dBm at
  0.6 kbps
• Programmable Data Rate from 0.6 to 600 kbps
• Frequency Bands: 300–348 MHz,
  387–464 MHz, and 779–928 MHz
• 2-FSK, 4-FSK, GFSK, MSK, and OOK Supported
• Digital Features
• Flexible Support for Packet Oriented Systems
• On-chip Support for Sync Word Detection, Flexible Packet Length, and Automatic CRC Calculation
• Low-Power Features
• 200-nA Sleep Mode Current Consumption
• Fast Startup Time; 240 μs From Sleep to RX Mode
• 64-Byte RX FIFO
• General
• Few External Components; Completely On-chip Frequency Synthesizer, No External Filters or RF Switch Needed
• Green Package: RoHS Compliant and No Antimony or Bromine
• Small Size (QLP 4- x 4-mm Package, 20 Pins)
• Suited for Systems Targeting Compliance with EN 300 220 (Europe) and FCC CFR Part 15 (US)
• Support for Asynchronous and Synchronous Serial Transmit Mode for Backward Compatibility with Existing Radio Communication Protocols

1.2 Applications

• Ultra Low-Power Wireless Applications Operating in the 315-, 433-, 868-, 915-MHz ISM or SRD Bands
• Wireless Alarm and Security Systems
• Industrial Monitoring and Control
• Remote Controls
• Toys
• Home and Building Automation

1.3 Description

The CC113L is a cost optimized sub-1 GHz RF receiver for the 300–348 MHz, 387–464 MHz, and 779–928 MHz frequency bands. The circuit is based on the popular CC1101 RF transceiver, and RF performance characteristics are identical. The CC115L transmitter together with the CC113L receiver enable a low-cost RF link.

The RF receiver is integrated with a highly configurable baseband demodulator. The modem supports various modulation formats and has a configurable data rate up to 600 kbps.

The CC113L provides extensive hardware support for packet handling, data buffering, and burst transmissions.

The main operating parameters and the 64-byte receive FIFO of CC113L can be controlled through a serial peripheral interface (SPI). In a typical system, the CC113L will be used together with a microcontroller and a few additional passive components.

1.4 Functional Block Diagram

Figure 1-1 shows a functional block diagram of the device.

Figure 1-1 Functional Block Diagram

3.1 Pin Diagram

The CC113L pinout is shown in Figure 3-1 and Table 3-1. See Section 5.18 for details on the I/O configuration.

Figure 3-1 Pinout Top View

3.2 Signal Descriptions