SWRS181D September   2015  – July 2018 CC1310

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram – RSM Package
    2. 4.2 Signal Descriptions – RSM Package
    3. 4.3 Pin Diagram – RHB Package
    4. 4.4 Signal Descriptions – RHB Package
    5. 4.5 Pin Diagram – RGZ Package
    6. 4.6 Signal Descriptions – RGZ Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  RF Characteristics
    6. 5.6  Receive (RX) Parameters, 861 MHz to 1054 MHz
    7. 5.7  Receive (RX) Parameters, 431 MHz to 527 MHz
    8. 5.8  Transmit (TX) Parameters, 861 MHz to 1054 MHz
    9. 5.9  Transmit (TX) Parameters, 431 MHz to 527 MHz
    10. 5.10 PLL Parameters
    11. 5.11 ADC Characteristics
    12. 5.12 Temperature Sensor
    13. 5.13 Battery Monitor
    14. 5.14 Continuous Time Comparator
    15. 5.15 Low-Power Clocked Comparator
    16. 5.16 Programmable Current Source
    17. 5.17 DC Characteristics
    18. 5.18 Thermal Characteristics
    19. 5.19 Timing and Switching Characteristics
      1. 5.19.1 Reset Timing
        1. Table 5-1 Reset Timing
      2. 5.19.2 Wakeup Timing
        1. Table 5-2 Wakeup Timing
      3. 5.19.3 Clock Specifications
        1. Table 5-3 24-MHz Crystal Oscillator (XOSC_HF)
        2. Table 5-4 32.768-kHz Crystal Oscillator (XOSC_LF)
        3. Table 5-5 48-MHz RC Oscillator (RCOSC_HF)
        4. Table 5-6 32-kHz RC Oscillator (RCOSC_LF)
      4. 5.19.4 Flash Memory Characteristics
        1. Table 5-7 Flash Memory Characteristics
      5. 5.19.5 Synchronous Serial Interface (SSI) Characteristics
        1. Table 5-8 Synchronous Serial Interface (SSI) Characteristics
    20. 5.20 Typical Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Main CPU
    3. 6.3  RF Core
    4. 6.4  Sensor Controller
    5. 6.5  Memory
    6. 6.6  Debug
    7. 6.7  Power Management
    8. 6.8  Clock Systems
    9. 6.9  General Peripherals and Modules
    10. 6.10 Voltage Supply Domains
    11. 6.11 System Architecture
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
    4. 8.4  Texas Instruments Low-Power RF Website
    5. 8.5  Additional Information
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Main CPU

The CC1310 SimpleLink Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the application and the higher layers of the protocol stack.

The CM3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

The CM3 features include the following:

  • 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
  • Outstanding processing performance combined with fast interrupt handling
  • ARM Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications:
    • Single-cycle multiply instruction and hardware divide
    • Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control
    • Unaligned data access, enabling data to be efficiently packed into memory
  • Fast code execution permits slower processor clock or increases sleep mode time
  • Harvard architecture characterized by separate buses for instruction and data
  • Efficient processor core, system, and memories
  • Hardware division and fast digital-signal-processing oriented multiply accumulate
  • Saturating arithmetic for signal processing
  • Deterministic, high-performance interrupt handling for time-critical applications
  • Enhanced system debug with extensive breakpoint and trace capabilities
  • Serial wire trace reduces the number of pins required for debugging and tracing
  • Migration from the ARM7™ processor family for better performance and power efficiency
  • Optimized for single-cycle flash memory use
  • Ultra-low power consumption with integrated sleep modes
  • 1.25 DMIPS per MHz