SWRS251A May   2021  – November 2021 CC1352P7

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram – RGZ Package (Top View)
    2. 6.2 Signal Descriptions – RGZ Package
    3. 6.3 Connections for Unused Pins and Modules
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power Supply and Modules
    5. 7.5  Power Consumption - Power Modes
    6. 7.6  Power Consumption - Radio Modes
    7. 7.7  Nonvolatile (Flash) Memory Characteristics
    8. 7.8  Thermal Resistance Characteristics
    9. 7.9  RF Frequency Bands
    10. 7.10 861 MHz to 1054 MHz - Receive (RX)
    11. 7.11 861 MHz to 1054 MHz - Transmit (TX) 
    12. 7.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
    13. 7.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
    14. 7.14 Bluetooth Low Energy - Receive (RX)
    15. 7.15 Bluetooth Low Energy - Transmit (TX)
    16. 7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
    17. 7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
    18. 7.18 Timing and Switching Characteristics
      1. 7.18.1 Reset Timing
      2. 7.18.2 Wakeup Timing
      3. 7.18.3 Clock Specifications
        1. 7.18.3.1 48 MHz Crystal Oscillator (XOSC_HF)
        2. 7.18.3.2 48 MHz RC Oscillator (RCOSC_HF)
        3. 7.18.3.3 2 MHz RC Oscillator (RCOSC_MF)
        4. 7.18.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
        5. 7.18.3.5 32 kHz RC Oscillator (RCOSC_LF)
      4. 7.18.4 Synchronous Serial Interface (SSI) Characteristics
        1. 7.18.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       40
      5. 7.18.5 UART
        1. 7.18.5.1 UART Characteristics
    19. 7.19 Peripheral Characteristics
      1. 7.19.1 ADC
        1. 7.19.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 7.19.2 DAC
        1. 7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 7.19.3 Temperature and Battery Monitor
        1. 7.19.3.1 Temperature Sensor
        2. 7.19.3.2 Battery Monitor
      4. 7.19.4 Comparators
        1. 7.19.4.1 Low-Power Clocked Comparator
        2. 7.19.4.2 Continuous Time Comparator
      5. 7.19.5 Current Source
        1. 7.19.5.1 Programmable Current Source
      6. 7.19.6 GPIO
        1. 7.19.6.1 GPIO DC Characteristics
    20. 7.20 Typical Characteristics
      1. 7.20.1 MCU Current
      2. 7.20.2 RX Current
      3. 7.20.3 TX Current
      4. 7.20.4 RX Performance
      5. 7.20.5 TX Performance
      6. 7.20.6 ADC Performance
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Proprietary Radio Formats
      2. 8.3.2 Bluetooth 5.2 Low Energy
      3. 8.3.3 802.15.4 (Thread, Zigbee, 6LoWPAN)
    4. 8.4  Memory
    5. 8.5  Sensor Controller
    6. 8.6  Cryptography
    7. 8.7  Timers
    8. 8.8  Serial Peripherals and I/O
    9. 8.9  Battery and Temperature Monitor
    10. 8.10 µDMA
    11. 8.11 Debug
    12. 8.12 Power Management
    13. 8.13 Clock Systems
    14. 8.14 Network Processor
  9. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
      1. 10.2.1 SimpleLink™ Microcontroller Platform
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 8 KB
Supported flash erase cycles before failure, single-bank(1)(5) 30 k Cycles
Supported flash erase cycles before failure, single sector(2) 60 k Cycles
Maximum number of write operations per row before sector erase(3) 83 Write Operations
Flash retention 105 °C 11.4 Years at 105 °C
Flash sector erase current Average delta current 9.5 mA
Flash sector erase time(4) Zero cycles 10 ms
30k cycles 4000 ms
Flash write current Average delta current, 4 bytes at a time 5.2 mA
Flash write time(4) 4 bytes at a time 21.6 µs
(1) A full bank erase is counted as a single erase cycle on each sector. If both flash banks are always cycled simultaneously they can be cycled 30K times each. Alternatively, the banks can be cycled a total of 30K times, e.g. the main bank X times and the second bank Y times (X+Y=30K)
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.