SWRS070B March   2008  – September 2014 CC2591

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Handling Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Electrical Characteristics
    5. 4.5 Thermal Resistance Characteristics for RGV Package
    6. 4.6 Typical Characteristics
  5. 5Applications, Implementation, and Layout
    1. 5.1 CC2591EM Evaluation Module
    2. 5.2 Controlling the Output Power from CC2591
      1. 5.2.1 Input Levels on Control Pins
      2. 5.2.2 Connecting CC2591 to a CC24xx Device
      3. 5.2.3 Connecting CC2591 to the CC2500, CC2510, or CC2511 Device
      4. 5.2.4 Connecting CC2591 to a CC2520 Device
  6. 6Device and Documentation Support
    1. 6.1 Device Support
      1. 6.1.1 Development Support
      2. 6.1.2 Device Nomenclature
    2. 6.2 Documentation Support
      1. 6.2.1 Community Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Export Control Notice
    6. 6.6 Glossary
  7. 7Mechanical Packaging and Orderable Information
    1. 7.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Terminal Configuration and Functions

The CC2591 pinout and description are shown in Figure 3-1 and Table 3-1, respectively.

po_wrs070.gifFigure 3-1 PIN AND I/O CONFIGURATION (TOP VIEW)

NOTE

The exposed die attach pad must be connected to a solid ground plane as this is the primary ground connection for the chip. Inductance in vias to the pad should be minimized. It is highly recommended to follow the reference layout. Changes will alter the performance.

For best performance, minimize the length of the ground vias, by using a 4-layer PCB with ground plane as layer 2 when CC2591 is mounted onto layer 1.

3.1 Pin Attributes

Table 3-1 Pin Attributes

TERMINAL TYPE DESCRIPTION
NO. NAME
— GND Ground The exposed die attach pad must be connected to a solid ground plane. See CC2591EM reference design for recommended layout.
1 AVDD_PA1 Power 2.0 V – 3.6 V Power. PCB trace to this pin serves as inductive load to PA . See CC2591EM reference design for recommended layout.
2 RF_N RF RF interface towards CC24xx or CC25xx device.
3 RXTX Analog/Control RXTX switching voltage when connected to CC24xx devices. See Table 5-2 and Table 5-3 for details.
4 RF_P RF RF interface towards CC24xx or CC25xx device
5 PAEN Digital Input Digital control pin. See Table 5-2 and Table 5-3 for details.
6 EN Digital Input Digital control pin. See Table 5-2 and Table 5-3 for details.
7 HGM Digital Input Digital control pin.
HGM=1 → Device in High Gain Mode
HGM=0 → Device in Low Gain Mode (RX only)
8, 9, 12, 14 GND Ground Secondary ground connections. Should be shorted to the die attach pad on the top PCB layer.
10 AVDD_PA2 Power 2.0 V – 3.6 V Power. PCB trace to this pin serves as inductive load to PA. See CC2591EM reference design for recommended layout.
11 ANT RF Antenna interface.
13 AVDD_LNA Power 2 V – 3.6 V Power. PCB trace to this pin serves as inductive load to LNA. See CC2591EM reference design for recommended layout.
15 BIAS Analog Biasing input. Resistor between this node and ground sets bias current to PAs.
16 AVDD_BIAS Power 2 V – 3.6 V Power.