SWRS194J January   2018  – November 2023 CC2642R

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RGZ Package (Top View)
    2. 7.2 Signal Descriptions – RGZ Package
    3. 7.3 Connections for Unused Pins and Modules
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  RF Frequency Bands
    10. 8.10 Bluetooth Low Energy - Receive (RX)
    11. 8.11 Bluetooth Low Energy - Transmit (TX)
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1 Reset Timing
      2. 8.12.2 Wakeup Timing
      3. 8.12.3 Clock Specifications
        1. 8.12.3.1 48 MHz Crystal Oscillator (XOSC_HF)
        2. 8.12.3.2 48 MHz RC Oscillator (RCOSC_HF)
        3. 8.12.3.3 2 MHz RC Oscillator (RCOSC_MF)
        4. 8.12.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
        5. 8.12.3.5 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.12.4 Synchronous Serial Interface (SSI) Characteristics
        1. 8.12.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       35
      5. 8.12.5 UART
        1. 8.12.5.1 UART Characteristics
    13. 8.13 Peripheral Characteristics
      1. 8.13.1 ADC
        1. 8.13.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 8.13.2 DAC
        1. 8.13.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.13.3 Temperature and Battery Monitor
        1. 8.13.3.1 Temperature Sensor
        2. 8.13.3.2 Battery Monitor
      4. 8.13.4 Comparators
        1. 8.13.4.1 Low-Power Clocked Comparator
        2. 8.13.4.2 Continuous Time Comparator
      5. 8.13.5 Current Source
        1. 8.13.5.1 Programmable Current Source
      6. 8.13.6 GPIO
        1. 8.13.6.1 GPIO DC Characteristics
    14. 8.14 Typical Characteristics
      1. 8.14.1 MCU Current
      2. 8.14.2 RX Current
      3. 8.14.3 TX Current
      4. 8.14.4 RX Performance
      5. 8.14.5 TX Performance
      6. 8.14.6 ADC Performance
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Bluetooth 5.2 Low Energy
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems
    14. 9.14 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  12. 11Device and Documentation Support
    1. 11.1 Tools and Software
      1. 11.1.1 SimpleLink™ Microcontroller Platform
    2. 11.2 Documentation Support
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.13.2.1 Digital-to-Analog Converter (DAC) Characteristics

Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Resolution 8 Bits
VDDS Supply voltage Any load, any VREF, pre-charge OFF, DAC charge-pump ON 1.8 3.8 V
External Load(4), any VREF, pre-charge OFF, DAC charge-pump OFF 2.0 3.8
Any load, VREF = DCOUPL, pre-charge ON 2.6 3.8
FDAC Clock frequency Buffer ON (recommended for external load) 16 250 kHz
Buffer OFF (internal load) 16 1000
Voltage output settling time VREF = VDDS, buffer OFF, internal load 13 1 / FDAC
VREF = VDDS, buffer ON, external capacitive load = 20 pF(3) 13.8
External capacitive load 20 200 pF
External resistive load 10 MΩ
Short circuit current 400 µA
ZMAX Max output impedance Vref = VDDS, buffer ON, CLK 250 kHz (5) VDDS = 3.8 V, DAC charge-pump OFF 50.8 kΩ
VDDS = 3.0 V, DAC charge-pump ON 51.7
VDDS = 3.0 V, DAC charge-pump OFF 53.2
VDDS = 2.0 V, DAC charge-pump ON 48.7
VDDS = 2.0 V, DAC charge-pump OFF 70.2
VDDS = 1.8 V, DAC charge-pump ON 46.3
VDDS = 1.8 V, DAC charge-pump OFF 88.9
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
DNL Differential nonlinearity VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked Comparator
FDAC = 250 kHz		 ±1 LSB(1)
Differential nonlinearity VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked Comparator
FDAC = 16 kHz		 ±1.2
Offset error(2)
Load = Continuous Time Comparator		 VREF = VDDS = 3.8 V ±0.64 LSB(1)
VREF = VDDS = 3.0 V ±0.81
VREF = VDDS = 1.8 V ±1.27
VREF = DCOUPL, pre-charge ON ±3.43
VREF = DCOUPL, pre-charge OFF ±2.88
VREF = ADCREF ±2.37
Offset error(2)
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V ±0.78 LSB(1)
VREF = VDDS = 3.0 V ±0.77
VREF = VDDS = 1.8 V ±3.46
VREF = DCOUPL, pre-charge ON ±3.44
VREF = DCOUPL, pre-charge OFF ±4.70
VREF = ADCREF ±4.11
Max code output voltage variation(2)
Load = Continuous Time Comparator		 VREF = VDDS = 3.8 V ±1.53 LSB(1)
VREF = VDDS = 3.0 V ±1.71
VREF = VDDS = 1.8 V ±2.10
VREF = DCOUPL, pre-charge ON ±6.00
VREF = DCOUPL, pre-charge OFF ±3.85
VREF = ADCREF ±5.84
Max code output voltage variation(2)
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V ±2.92 LSB(1)
VREF =VDDS = 3.0 V ±3.06
VREF = VDDS = 1.8 V ±3.91
VREF = DCOUPL, pre-charge ON ±7.84
VREF = DCOUPL, pre-charge OFF ±4.06
VREF = ADCREF ±6.94
Output voltage range(2)
Load = Continuous Time Comparator		 VREF = VDDS = 3.8 V, code 1 0.03 V
VREF = VDDS = 3.8 V, code 255 3.62
VREF = VDDS = 3.0 V, code 1 0.02
VREF = VDDS = 3.0 V, code 255 2.86
VREF = VDDS = 1.8 V, code 1 0.01
VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.01
VREF = DCOUPL, pre-charge OFF, code 255 1.21
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46
VREF = ADCREF, code 1 0.01
VREF = ADCREF, code 255 1.41
Output voltage range(2)
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V, code 1 0.03 V
VREF = VDDS = 3.8 V, code 255 3.61
VREF = VDDS = 3.0 V, code 1 0.02
VREF = VDDS = 3.0 V, code 255 2.85
VREF = VDDS = 1.8 V, code 1 0.01
VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.01
VREF = DCOUPL, pre-charge OFF, code 255 1.21
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46
VREF = ADCREF, code 1 0.01
VREF = ADCREF, code 255 1.41
External Load (Keysight 34401A Multimeter)
INL Integral nonlinearity VREF = VDDS, FDAC = 250 kHz ±1 LSB(1)
VREF = DCOUPL, FDAC = 250 kHz ±1
VREF = ADCREF, FDAC = 250 kHz ±1
DNL Differential nonlinearity VREF = VDDS, FDAC = 250 kHz ±1 LSB(1)
Offset error VREF = VDDS = 3.8 V ±0.40 LSB(1)
VREF = VDDS = 3.0 V ±0.50
VREF = VDDS = 1.8 V ±0.75
VREF = DCOUPL, pre-charge ON ±1.55
VREF = DCOUPL, pre-charge OFF ±1.30
VREF = ADCREF ±1.10
Max code output voltage variation VREF = VDDS = 3.8 V ±1.00 LSB(1)
VREF = VDDS = 3.0 V ±1.00
VREF = VDDS = 1.8 V ±1.00
VREF = DCOUPL, pre-charge ON ±3.45
VREF = DCOUPL, pre-charge OFF ±2.10
VREF = ADCREF ±1.90
Output voltage range
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V, code 1 0.03 V
VREF = VDDS = 3.8 V, code 255 3.61
VREF = VDDS = 3.0 V, code 1 0.02
VREF = VDDS = 3.0 V, code 255 2.85
VREF = VDDS = 1.8 V, code 1 0.02
VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.02
VREF = DCOUPL, pre-charge OFF, code 255 1.20
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46
VREF = ADCREF, code 1 0.02
VREF = ADCREF, code 255 1.42
(1) 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset
(3) A load > 20 pF will increases the settling time
(4) Keysight 34401A Multimeter
(5) When using lower levels of VDDS with the charge pump OFF, care must be taken to adapt the surrounding circuit to the increase in impedance.