SWRS207J January 2018 – November 2023 CC2652R
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | 0 | VDDS | V | ||
Clock frequency | SCLK_LF | ||||
Internal reference voltage(1) | Using internal DAC with VDDS as reference voltage, DAC code = 0 - 255 | 0.024 - 2.865 | V | ||
Offset | Measured at VDDS / 2, includes error from internal DAC | ±5 | mV | ||
Decision time | Step from –50 mV to 50 mV | 1 | Clock Cycle |