SWRS269A december   2022  – june 2023 CC2674P10

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RGZ Package (Top View)
    2. 7.2 Signal Descriptions – RGZ Package
    3. 7.3 Connections for Unused Pins and Modules – RGZ Package
    4. 7.4 Pin Diagram – RSK Package (Top View)
    5. 7.5 Signal Descriptions – RSK Package
    6. 7.6 Connection of Unused Pins and Module – RSK Package
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  RF Frequency Bands
    10. 8.10 Bluetooth Low Energy - Receive (RX)
    11. 8.11 Bluetooth Low Energy - Transmit (TX)
    12. 8.12 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
    13. 8.13 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Reset Timing
      2. 8.14.2 Wakeup Timing
      3. 8.14.3 Clock Specifications
        1. 8.14.3.1 48 MHz Clock Input (TCXO)
        2. 8.14.3.2 48 MHz Crystal Oscillator (XOSC_HF)
        3. 8.14.3.3 48 MHz RC Oscillator (RCOSC_HF)
        4. 8.14.3.4 2 MHz RC Oscillator (RCOSC_MF)
        5. 8.14.3.5 32.768 kHz Crystal Oscillator (XOSC_LF)
        6. 8.14.3.6 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.14.4 Serial Peripheral Interface (SPI) Characteristics
        1. 8.14.4.1 SPI Characteristics
        2. 8.14.4.2 SPI Master Mode
        3. 8.14.4.3 SPI Master Mode Timing Diagrams
        4. 8.14.4.4 SPI Slave Mode
        5. 8.14.4.5 SPI Slave Mode Timing Diagrams
      5. 8.14.5 UART
        1. 8.14.5.1 UART Characteristics
    15. 8.15 Peripheral Characteristics
      1. 8.15.1 ADC
        1. 8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 8.15.2 DAC
        1. 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.15.3 Temperature and Battery Monitor
        1. 8.15.3.1 Temperature Sensor
        2. 8.15.3.2 Battery Monitor
      4. 8.15.4 Comparators
        1. 8.15.4.1 Low-Power Clocked Comparator
        2. 8.15.4.2 Continuous Time Comparator
      5. 8.15.5 Current Source
        1. 8.15.5.1 Programmable Current Source
      6. 8.15.6 GPIO
        1. 8.15.6.1 GPIO DC Characteristics
    16. 8.16 Typical Characteristics
      1. 8.16.1 MCU Current
      2. 8.16.2 RX Current
      3. 8.16.3 TX Current
      4. 8.16.4 RX Performance
      5. 8.16.5 TX Performance
      6. 8.16.6 ADC Performance
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Bluetooth 5.3 Low Energy
      2. 9.3.2 802.15.4 Thread, Zigbee, and 6LoWPAN
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems
    14. 9.14 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
  12. 11Device and Documentation Support
    1. 11.1 Tools and Software
      1. 11.1.1 SimpleLink™ Microcontroller Platform
    2. 11.2 Documentation Support
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.14.4.4 SPI Slave Mode

over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
tCS.LEAD CS lead-time, CS active to clock 1 SCLK
tCS.LAG CS lag time, Last clock to CS inactive 1 SCLK
tCS.ACC CS access time, CS active to MISO data out VDDS = 3.3V 56 ns
tCS.ACC CS access time, CS active to MISO data out VDDS = 1.8V 70 ns
tCS.DIS CS disable time, CS inactive to MISO high inpedance VDDS = 3.3V 56 ns
tCS.DIS CS disable time, CS inactive to MISO high inpedance VDDS = 1.8V 70 ns
tSU.SI MOSI input data setup time 30 ns
tHD.SI MOSI input data hold time 0 ns
tVALID.SO MISO output data valid time(1) SCLK edge to MISO valid,CL = 20 pF, 3.3V (4) 50 ns
tVALID.SO MISO output data valid time(1) SCLK edge to MISO valid,CL = 20 pF, 1.8V (4) 65 ns
tHD.SO MISO output data hold time(2) CL = 20 pF 0 ns
(1)
Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(2)
Specifies how long data on the output is valid after the output changing SCLK clock edge