SWRS304A October   2024  – December 2024 CC2745P10-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram—RHA package
    2. 6.2 Signal Descriptions—RHA Package
    3. 6.3 Connections for Unused Pins and Modules—RHA Package
    4. 6.4 RHA Peripheral Pin Mapping
    5. 6.5 RHA Peripheral Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD and MSL Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  DC/DC
    5. 7.5  GLDO
    6. 7.6  Power Supply and Modules
    7. 7.7  Battery Monitor
    8. 7.8  BATMON Temperature Sensor
    9. 7.9  Power Consumption—Power Modes
    10. 7.10 Power Consumption—Radio Modes
    11. 7.11 Nonvolatile (Flash) Memory Characteristics
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 RF Frequency Bands
    14. 7.14 Bluetooth Low Energy—Receive (RX)
    15. 7.15 Bluetooth Low Energy—Transmit (TX)
    16. 7.16 Bluetooth Channel Sounding
    17. 7.17 2.4GHz RX/TX CW
    18. 7.18 Timing and Switching Characteristics
      1. 7.18.1 Reset Timing
      2. 7.18.2 Wakeup Timing
      3. 7.18.3 Clock Specifications
        1. 7.18.3.1 48 MHz Crystal Oscillator (HFXT)
        2. 7.18.3.2 96 MHz RC Oscillator (HFOSC)
        3. 7.18.3.3 80/90/98 MHz RC Oscillator (AFOSC)
        4. 7.18.3.4 32 kHz Crystal Oscillator (LFXT)
        5. 7.18.3.5 32 kHz RC Oscillator (LFOSC)
    19. 7.19 Peripheral Characteristics
      1. 7.19.1 UART
        1. 7.19.1.1 UART Characteristics
      2. 7.19.2 SPI
        1. 7.19.2.1 SPI Characteristics
        2. 7.19.2.2 SPI Controller Mode
        3. 7.19.2.3 SPI Timing Diagrams - Controller Mode
        4. 7.19.2.4 SPI Peripheral Mode
        5. 7.19.2.5 SPI Timing Diagrams - Peripheral Mode
      3. 7.19.3 I2C
        1. 7.19.3.1 I2C Characteristics
        2. 7.19.3.2 I2C Timing Diagram
      4. 7.19.4 I2S
        1. 7.19.4.1 I2S Controller Mode
        2. 7.19.4.2 I2S Peripheral Mode
      5. 7.19.5 CAN-FD
        1. 7.19.5.1 CAN-FD Characteristics
      6. 7.19.6 GPIO
        1. 7.19.6.1 GPIO DC Characteristics
      7. 7.19.7 ADC
        1. 7.19.7.1 Analog-to-Digital Converter (ADC) Characteristics
      8. 7.19.8 Comparators
        1. 7.19.8.1 Low Power Comparator
      9. 7.19.9 Voltage Glitch Monitor
    20. 7.20 Typical Characteristics
      1. 7.20.1 MCU Current
      2. 7.20.2 RX Current
      3. 7.20.3 TX Current
      4. 7.20.4 RX Performance
      5. 7.20.5 TX Performance
      6. 7.20.6 ADC Performance
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Bluetooth Low Energy
    4. 8.4  Memory
    5. 8.5  Hardware Security Module (HSM)
    6. 8.6  Cryptography
    7. 8.7  Timers
    8. 8.8  Algorithm Processing Unit (APU)
    9. 8.9  Serial Peripherals and I/O
    10. 8.10 Battery and Temperature Monitor
    11. 8.11 Voltage Glitch Monitor (VGM)
    12. 8.12 µDMA
    13. 8.13 Debug
    14. 8.14 Power Management
    15. 8.15 Clock Systems
    16. 8.16 Network Processor
    17. 8.17 Integrated BALUN, High Power PA (Power Amplifier)
  10. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
      1. 10.2.1 SimpleLink™ Microcontroller Platform
      2. 10.2.2 Software License and Notice
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Hardware Security Module (HSM)

The CC27xx devices have an integrated hardware security module (HSM) supporting an isolated environment for cryptographic, key management, secure counters, and random number generation operations. Selected algorithms are protected from differential power analysis (DPA) side channel attacks. Together with a large selection of open-source cryptography libraries provided with the Software Development Kit (SDK), the system enables secure and future proof automotive and IoT applications to be easily built on the platform.

The following cryptographic functions using energy efficient accelerators and RNG functions are accelerated by the HSM:

  • Key Agreement Schemes
    • Elliptic Curve Diffie-Hellman with static or ephemeral keys (ECDH and ECDHE)
    • Diffie Hellman with static or ephemeral keys (DH and DHE)
  • Signature Processing
    • Elliptic Curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
    • Edwards-Curve Digital Signature Algorithm (EdDSA)
    • RSA PKCS #1 v1.5
    • RSA PSS
  • Message Authentication Codes
    • AES CBC-MAC
    • AES CMAC
    • HMAC with SHA2-224, SHA2-256, SHA2-384, and SHA2-512
  • Block Cipher Modes of Operation
    • AES CCM and AES CCM* (CCM-Star)
    • AES GCM
    • AES ECB
    • AES CBC
    • AES CTR
  • Hash Algorithms
    • SHA2-224
    • SHA2-256
    • SHA2-384
    • SHA2-512
  • Random Number Generation
    • TRNG (True Random Number Generator)
    • AES-CTR DRBG (Deterministic Random Bit Generator)

Cryptographic key sizes and types include:

  • Advanced Encryption Standard (AES) key sizes of 128, 192, and 256 bits
  • RSA key sizes up to 3072 bits (Sign and Verify supported), and up to 4096 bits (verify only)
  • Diffie-Hellman key sizes of 2048 bits and 3072 bits
  • Elliptic Curve Support
    • Short Weierstrass
      • NIST-P224 (secp224r1), NIST-P256 (secp256r1), NIST-P384 (secp384r1), NIST-P521 (secp521r1)
      • Brainpool-256R1, Brainpool-384R1, Brainpool-512R1
    • Montgomery
      • Curve25519
    • Twisted Edwards form
      • Ed25519

DPA countermeasures are implemented for:

  • AES operations
  • ECDSA operations

The HSM executes the HSM firmware from a secured flash region. 96KB of the device flash memory is reserved for the HSM firmware. The HSM firmware is verified by the HSM ROM during HSM boot process. Secure firmware update of the HSM firmware image on-chip is handled by the system ROM bootcode and the HSM ROM.

The HSM also has a data RAM region that is not accessible to the rest of the system (system CPU, DMA, debug access, and so on). The data RAM region is retained in low power modes, supporting quick power up of the HSM and retention of key material. In addition to the storage of key material in data RAM, the HSM supports importing and exporting wrapped key material (NIST SP800-38F) with a key unique to the device, known as a HW Unique Key (HUK). This allows keys to be securely stored anywhere in the system’s nonvolatile (Flash) memory.

The HSM is accessible to the application running on the system CPU in a controlled manner via the HSM mailbox interface. The HSM is a bus controller in the device and can access the system memory directly, enabling better efficiency for moving data during cryptographic operations.

The SimpleLink Low Power F3 software development kit (SDK) includes the encrypted and authenticated HSM firmware needed to be programmed on-chip for the HSM operation and drivers for all HSM functions.