SWRS304 October   2024 CC2745P10-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Functional Block Diagram
  6. 5Device Comparison
  7. 6Pin Configuration and Functions
    1. 6.1 Pin Diagram—RHA package
    2. 6.2 Signal Descriptions – RHA Package
    3. 6.3 Connections for Unused Pins and Modules—RHA Package
    4. 6.4 RHA Peripheral Pin Mapping
    5. 6.5 RHA Peripheral Signal Descriptions
  8. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
      1. 7.2.1 SimpleLink™ Microcontroller Platform
    3. 7.3 Documentation Support
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.2 Signal Descriptions – RHA Package

Table 6-1 Signal Descriptions—RHA Package
PINI/OTYPEDESCRIPTION
NAMENO.
VDDR1—PowerInternal supply, must be powered from the internal DC/DC converter or the internal LDO(1)(2)(3)
VDDR2—PowerInternal supply, must be powered from the internal DC/DC converter or the internal LDO(1)(2)(3)
DIO03I/ODigitalGPIO
DIO14I/ODigitalGPIO
DIO25I/ODigitalGPIO, high-drive capability
DIO36I/ODigitalGPIO, high-drive capability
DIO47I/ODigitalGPIO
DIO58I/ODigitalGPIO
VDDIO9—Power1.71V to 3.8V split rail I/O supply(4)
DIO710I/ODigitalGPIO
DIO9_SWDIO11I/ODigitalGPIO, SWD interface: mode select or SWDIO, high-drive capability
DIO10_SWDCK12I/ODigitalGPIO, SWD interface: clock, high-drive capability
DIO1113I/ODigitalGPIO
DIO1214I/ODigitalGPIO
DIO1515I/ODigitalGPIO
DIO1616I/ODigitalGPIO
VDDIO17—Power1.71V to 3.8V split rail I/O supply(4)
VDDS18—Power1.71V to 3.8V supply(4)
DIO17_A819I/ODigital or AnalogGPIO, analog capability, high-drive capability
DIO18_A720I/ODigital or AnalogGPIO, analog capability, high-drive capability
DIO19_A621I/ODigital or AnalogGPIO, analog capability
DIO20_A522I/ODigital or AnalogGPIO, analog capability
DIO21_A423I/ODigital or AnalogGPIO, analog capability
DIO22_A324I/ODigital or AnalogGPIO, analog capability
RSTN25IDigitalReset, active low. No internal pullup resistor
DIO23_X32P26I/ODigital or AnalogGPIO, 32kHz crystal oscillator pin 1, Optional TCXO input
DIO24_X32N27I/ODigital or AnalogGPIO, 32kHz crystal oscillator pin 2
VDDD28—PowerFor decoupling of internal 1.32V regulated core-supply. Connect an external 1μF decoupling capacitor.(1)
VDDS29—Power1.71V to 3.8V supply. Connect an external 10 μF decoupling capacitor.(4)
DCDC30—PowerSwitching node of internal DC/DC converter(4)
VDDS31—Power1.71V to 3.8V supply(4)
DIO27_A132I/ODigital or AnalogGPIO, analog capability
DIO28_A033I/ODigital or AnalogGPIO, analog capability
VDDR34—PowerInternal supply, must be powered from the internal DC/DC converter or the internal LDO. Connect an external 10 μF decoupling capacitor.(1)(2)(3)
X48P35—Analog48MHz crystal oscillator pin 1
X48N36—Analog48MHz crystal oscillator pin 2
NC37——No Connect
VDDS38—Power1.71V to 3.8V supply(4)
ANT39—RF2.4GHz TX, RX
NC40——

No Connect (6)

EGP

——GNDGround – exposed ground pad(5)
(1) Do not supply external circuitry from this pin.
(2) VDDR pins 1, 2, and 34 must be tied together on the PCB.
(3) Output from internal DC/DC and LDO is trimmed to 1.5V.
(4) For more details, see the technical reference manual listed in Documentation Support.
(5) EPG is the only ground connection for the device. A good electrical connection to the device ground on a printed circuit board (PCB) is imperative for proper device operation.
(6) This pin is not connected to the die. In LP-EM-CC2745R10-Q1, LP-EM-CC2755P10 reference design, this pin is connected to the ground to give better shielding on the antenna path.