Completely Offloads Wi-Fi and Internet Protocols from the External Microcontroller
Connect any low-cost, low-power microcontroller (MCU) to the Internet of Things (IoT). The CC3100 device is the industry's first Wi-Fi CERTIFIED chip used in the wireless networking solution. The CC3100 device is part of the new SimpleLink Wi-Fi family that dramatically simplifies the implementation of Internet connectivity. The CC3100 device integrates all protocols for Wi-Fi and Internet, which greatly minimizes host MCU software requirements. With built-in security protocols, the CC3100 solution provides a robust and simple security experience. Additionally, the CC3100 device is a complete platform solution including various tools and software, sample applications, user and programming guides, reference designs and the TI E2E™ support community. The CC3100 device is available in an easy-to-layout QFN package.
The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a-Chip and contains an additional dedicated ARM MCU that completely offloads the host MCU. This subsystem includes an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit encryption. The CC3100 device supports Station, Access Point, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. This subsystem includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols.
The power-management subsystem includes integrated DC-DC converters supporting a wide range of supply voltages. This subsystem enables low-power consumption modes, such as the hibernate with RTC mode requiringabout 4 μA of current.
The CC3100 device can connect to any 8, 16, or 32-bit MCU over the SPI or UART Interface. The device driver minimizes the host memory footprint requirements requiring less than 7KB of code memory and 700 B of RAM memory for a TCP client application.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
CC3100R11MRGCR/T | QFN (64) | 9.0 mm x 9.0 mm |
Figure 1-1 shows the CC3100 hardware overview.
Figure 1-2 shows an overview of the CC3100 embedded software.
Changes from C Revision (August 2014) to D Revision
Figure 3-1 shows pin assignments for the 64-pin QFN package.
Table 3-1 describes the CC3100 pins.
NOTE
If an external device drives a positive voltage to signal pads when the CC3100 device is not powered, DC current is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3100 device can occur. To prevent current draw, TI recommends one of the following:
PIN | DEFAULT FUNCTION | STATE AT RESET AND HIBERNATE | I/O TYPE | DESCRIPTION |
---|---|---|---|---|
1 | NC | Hi-Z | N/A | Unused; leave unconnected. |
2 | nHIB | Hi-Z | I | Hibernate signal input to the NWP (active low). This is connected to the MCU GPIO. If the GPIO from the MCU can float while the MCU enters low power, consider adding a pull-up resistor on the board to avoid floating. |
3 | Reserved | Hi-Z | NA | Reserved for future use |
4 | FORCE_AP | Hi-Z | I | For forced AP mode, pull to high on the board using 100k resistor. Otherwise, pull down to ground using 100k resistor.(1) |
5 | HOST_SPI_CLK | Hi-Z | I | Host interface SPI clock |
6 | HOST_SPI_MOSI | Hi-Z | I | Host interface SPI data input |
7 | HOST_SPI_MISO | Hi-Z | O | Host interface SPI data output |
8 | HOST_SPI_nCS | Hi-Z | I | Host interface SPI chip select (active low) |
9 | VDD_DIG1 | Hi-Z | Power | Digital core supply (1.2 V) |
10 | VIN_IO1 | Hi-Z | Power | I/O supply |
11 | FLASH_SPI_CLK | Hi-Z | O | Serial flash interface: SPI clock |
12 | FLASH_SPI_MOSI | Hi-Z | O | Serial flash interface: SPI data out |
13 | FLASH _SPI_MISO (active high) |
Hi-Z | I | Serial flash interface: SPI data in |
14 | FLASH _SPI_nCS | Hi-Z | O | Serial flash interface: SPI chip select (active low) |
15 | HOST_INTR | Hi-Z | O | Interrupt output (active high) |
16 | NC | Hi-Z | N/A | Unused; leave unconnected. |
17 | NC | Hi-Z | N/A | Unused; leave unconnected. |
18 | NC | Hi-Z | N/A | Unused; leave unconnected. |
19 | Reserved | Hi-Z | N/A | Connect 100K pull-down to ground. |
20 | NC | Hi-Z | N/A | Unused; leave unconnected. |
21 | SOP2/TCXO_EN | Hi-Z | O | Enable signal for external TCXO. Add 10k pulldown to ground. |
22 | WLAN_XTAL_N | Hi-Z | Analog | Connect the WLAN 40-MHz XTAL here. |
23 | WLAN_XTAL_P | Hi-Z | Analog | Connect the WLAN 40-MHz XTAL here. |
24 | VDD_PLL | Hi-Z | Power | Internal PLL power supply (1.4 V nominal) |
25 | LDO_IN2 | Hi-Z | Power | Input to internal LDO |
26 | NC | Hi-Z | N/A | Unused; leave unconnected. |
27 | NC | Hi-Z | N/A | Unused; leave unconnected. |
28 | NC | Hi-Z | N/A | Unused; leave unconnected. |
29 | Reserved | Hi-Z | O | Reserved for future use |
30 | Reserved | Hi-Z | O | Reserved for future use |
31 | RF_BG | Hi-Z | RF | 2.4-GHz RF TX/RX |
32 | nRESET | Hi-Z | I | RESET input for the device. Active low input. Use RC circuit (100k || 0.1 µF) for power on reset. |
33 | VDD_PA_IN | Hi-Z | Power | Power supply for the RF power amplifier (PA) |
34 | SOP1 | Hi-Z | N/A | Add 100K pulldown to ground. |
35 | SOP0 | Hi-Z | N/A | Add 100K pulldown to ground. |
36 | LDO_IN1 | Hi-Z | Power | Input to internal LDO |
37 | VIN_DCDC_ANA | Hi-Z | Power | Power supply for the DC-DC converter for analog section |
38 | DCDC_ANA_SW | Hi-Z | Power | Analog DC-DC converter switch output |
39 | VIN_DCDC_PA | Hi-Z | Power | PA DC-DC converter input supply |
40 | DCDC_PA_SW_P | Hi-Z | Power | PA DC-DC converter switch output +ve |
41 | DCDC_PA_SW_N | Hi-Z | Power | PA DC-DC converter switch output –ve |
42 | DCDC_PA_OUT | Hi-Z | Power | PA DC-DC converter output. Connect the output capacitor for DC-DC here. |
43 | DCDC_DIG_SW | Hi-Z | Power | Digital DC-DC converter switch output |
44 | VIN_DCDC_DIG | Hi-Z | Power | Power supply input for the digital DC-DC converter |
45 | DCDC_ANA2_SW_P | Hi-Z | Power | Analog2 DC-DC converter switch output +ve |
46 | DCDC_ANA2_SW_N | Hi-Z | Power | Analog2 DC-DC converter switch output –ve |
47 | VDD_ANA2 | Hi-Z | Power | Analog2 power supply input |
48 | VDD_ANA1 | Hi-Z | Power | Analog1 power supply input |
49 | VDD_RAM | Hi-Z | Power | Power supply for the internal RAM |
50 | UART1_nRTS | Hi-Z | O | UART host interface |
51 | RTC_XTAL_P | Hi-Z | Analog | 32.768 kHz XTAL_P/external CMOS level clock input |
52 | RTC_XTAL_N | Hi-Z | Analog | 32.768 kHz XTAL_N/100k external pullup for external clock |
53 | NC | Hi-Z | N/A | Unused. Leave unconnected. |
54 | VIN_IO2 | Hi-Z | Power | I/O power supply. Same as battery voltage. |
55 | UART1_TX | Hi-Z | O | UART host interface. Connect to test point on prototype for flash programming. |
56 | VDD_DIG2 | Hi-Z | Power | Digital power supply (1.2 V) |
57 | UART1_RX | Hi-Z | I | UART host interface. Connect to test point on prototype for flash programming. |
58 | TEST_58 | N/A | Test signal. Connect to an external test point. | |
59 | TEST_59 | N/A | Test signal. Connect to an external test point. | |
60 | TEST_60 | Hi-Z | O | Test signal. Connect to an external test point. |
61 | UART1_nCTS | Hi-Z | I | UART host interface |
62 | TEST_62 | Hi-Z | O | Test signal. Connect to an external test point. |
63 | NC | Hi-Z | I/O | Leave unconnected |
64 | NC | Hi-Z | I/O | Leave unconnected |
65 | GND | Power | Ground tab used as thermal and electrical ground |
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over process and voltage, unless otherwise indicated.
PARAMETERS | PINS | MIN | MAX | UNIT |
---|---|---|---|---|
VBAT and VIO | 37, 39, 44 | –0.5 | 3.8 | V |
VIO-VBAT (differential) | 10, 54 | 0.0 | V | |
Digital inputs | –0.5 | VIO + 0.5 | V | |
RF pins | –0.5 | 2.1 | V | |
Analog pins (XTAL) | –0.5 | 2.1 | V | |
Operating temperature range (TA ) | –40 | +85 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –55 | +125 | °C | |
VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –2000 | +2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –500 | +500 | V |
CONDITIONS | POH | |
---|---|---|
TAmbient up to 85°C, assuming 20% active mode and 80% sleep mode | 17,500(1) |
PARAMETERS | PINS | CONDITIONS(2)(3) | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
VBAT, VIO (shorted to VBAT) | 10, 37, 39, 44, 54 | Direct battery connection | 2.1 | 3.3 | 3.6 | V |
VBAT, VIO (shorted to VBAT) | 10, 37, 39, 44, 54 | Preregulated 1.85 V | 1.76 | 1.85 | 1.9 | V |
Ambient thermal slew | –20 | 20 | °C/minute |
The device enters a brown-out condition whenever the input voltage dips below VBROWN (see Figure 4-1 and Figure 4-2). This condition must be considered during design of the power supply routing, especially if operating from a battery. High-current operations (such as a TX packet) cause a dip in the supply voltage, potentially triggering a brown-out. The resistance includes the internal resistance of the battery, contact resistance of the battery holder (4 contacts for a 2 x AA battery) and the wiring and PCB routing resistance.
In the brown-out condition, all sections of the device shut down except for the Hibernate module (including the 32-kHz RTC clock), which remains on. The current in this state can reach approximately 400 µA.
The black-out condition is equivalent to a hardware reset event in which all states within the device are lost.
Table 4-1 lists the brown-out and black-out voltage levels.
CONDITION | VOLTAGE LEVEL | UNIT |
---|---|---|
Vbrownout | 2.1 | V |
Vblackout | 1.67 | V |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
CIN | Pin capacitance | 4 | pF | ||||
VIH | High-level input voltage | 0.65 × VDD | VDD + 0.5 V | V | |||
VIL | Low-level input voltage | –0.5 | 0.35 × VDD | V | |||
IIH | High-level input current | 5 | nA | ||||
IIL | Low-level input current | 5 | nA | ||||
VOH | High-level output voltage (VDD = 3.0 V) |
2.4 | V | ||||
VOL | Low-level output voltage (VDD = 3.0 V) |
0.4 | V | ||||
IOH | High-level source current, VOH = 2.4 | 6 | mA | ||||
IOL | Low-level sink current, VOH = 0.4 | 6 | mA | ||||
Pin Internal Pullup and Pulldown (25°C) | |||||||
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | ||
IOH | Pull-Up current, VOH = 2.4 (VDD = 3.0 V) |
5 | 10 | µA | |||
IOL | Pull-Down current, VOL = 0.4 (VDD = 3.0 V) |
5 | µA | ||||
VIL | nRESET(1) | 0.6 | V |
Parameter | Condition (Mbps) | Min | Typ | Max | Units |
---|---|---|---|---|---|
Sensitivity (8% PER for 11b rates, 10% PER for 11g/11n rates)(10% PER)(2) |
1 DSSS | –95.7 | dBm | ||
2 DSSS | –93.6 | ||||
11 CCK | –88.0 | ||||
6 OFDM | –90.0 | ||||
9 OFDM | –89.0 | ||||
18 OFDM | –86.0 | ||||
36 OFDM | –80.5 | ||||
54 OFDM | –74.0 | ||||
MCS0 (GF)(1) | –89.0 | ||||
MCS7 (GF)(1) | –71.0 | ||||
Maximum input level (10% PER) |
802.11b | –4.0 | |||
802.11g | –10.0 |
Parameter | Condition(2) | Min | Typ | Max | Units |
---|---|---|---|---|---|
Maximum RMS output power measured at 1 dB from IEEE spectral mask or EVM | 1 DSSS | 18.0 | dBm | ||
2 DSSS | 18.0 | ||||
11 CCK | 18.3 | ||||
6 OFDM | 17.3 | ||||
9 OFDM | 17.3 | ||||
18 OFDM | 17.0 | ||||
36 OFDM | 16.0 | ||||
54 OFDM | 14.5 | ||||
MCS7 (MM) | 13.0 | ||||
Transmit center frequency accuracy | –25 | 25 | ppm |
PARAMETER | TEST CONDITIONS(1)(4) | MIN | TYP(5) | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|---|---|
TX | 1 DSSS | TX power level = 0 | 272 | mA | |||||
TX power level = 4 | 188 | ||||||||
6 OFDM | TX power level = 0 | 248 | |||||||
TX power level = 4 | 179 | ||||||||
54 OFDM | TX power level = 0 | 223 | |||||||
TX power level = 4 | 160 | ||||||||
RX(7) | 1 DSSS | 53 | |||||||
54 OFDM | 53 | ||||||||
Idle connected(2) | 0.690 | ||||||||
LPDS | 0.115 | ||||||||
Hibernate(6) | 4 | µA | |||||||
Peak calibration current (3)(7) | VBAT = 3.3 V | 450 | mA | ||||||
VBAT = 2.1 V | 670 | ||||||||
VBAT = 1.85 V | 700 |
AIR FLOW | ||||
---|---|---|---|---|
PARAMETER | 0 lfm (C/W) | 150 lfm (C/W) | 250 lfm (C/W) | 500 lfm (C/W) |
θja | 23 | 14.6 | 12.4 | 10.8 |
Ψjt | 0.2 | 0.2 | 0.3 | 0.1 |
Ψjb | 2.3 | 2.3 | 2.2 | 2.4 |
θjc | 6.3 | |||
θjb | 2.4 |
For proper operation of the CC3100 device, perform the recommended power-up sequencing as follows:
For timing diagrams, see Section 4.11.2, Reset Timing.
Figure 4-6 shows the reset timing diagram for the 32K XTAL first-time power-up and reset removal.
Table 4-2 describes the timing requirements for the 32K XTAL first-time power-up and reset removal.
Item | Name | Description | Min | Typ | Max |
---|---|---|---|---|---|
T1 | Supply settling time | Depends on application board power supply, decap, and so on | 3 ms | ||
T2 | Hardware wakeup time | 25 ms | |||
T3 | Initialization time | 32-kHz XTAL settling + firmware initialization time + radio calibration | 1.35 s |
Figure 4-7 shows the reset timing diagram for the external 32K first-time power-up and reset removal.
Table 4-3 describes the timing requirements for the external 32K first-time power-up and reset removal.
Item | Name | Description | Min | Typ | Max |
---|---|---|---|---|---|
T1 | Supply settling time | Depends on application board power supply, decap, and so on | 3 ms | ||
T2 | Hardware wakeup time | 25 ms | |||
T3 | Initialization time | Firmware initialization time + radio calibration | 250 ms |
Figure 4-8 shows the timing diagram for wakeup from the hibernate state.
NOTE
The 32.768-kHz XTAL is kept enabled by default when the chip goes to hibernate in response to nHIB being pulled low.
Table 4-4 describes the timing requirements for nHIB.
Item | Name | Description | Min | Typ | Max |
---|---|---|---|---|---|
Thib_min | Minimum hibernate time | Minimum pulse width of nHIB being low(2) | 10 ms | ||
Twake_from_hib | Hardware wakeup time plus firmware initialization time | See (1). | 50 ms |
The CC3100 device requires two separate clocks for its operation:
The device features internal oscillators that enable the use of cheaper crystals rather than dedicated TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system and reduce overall cost.
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance.
Figure 4-9 shows the crystal connections for the slow clock.
When an RTC clock oscillator is present in the system, the CC3100 device can accept this clock directly as an input. The clock is fed on the RTC_XTAL_P line and the RTC_XTAL_N line is held to VIO. The clock must be a CMOS-level clock compatible with VIO fed to the device.
Figure 4-10 shows the external RTC clock input connection.
The CC3100 device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The XTAL is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading capacitors.
Figure 4-11 shows the crystal connections for the fast clock.
The CC3100 device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the LDO improves noise on the TCXO power supply.
Figure 4-12 shows the connection.
Table 4-5 lists the external Fref clock requirements.
Characteristics | Condition | Sym | Min | Typ | Max | Unit | |
---|---|---|---|---|---|---|---|
Frequency | 40.00 | MHz | |||||
Frequency accuracy (Initial + temp + aging) | ±25 | ppm | |||||
Frequency input duty cycle | 45 | 50 | 55 | % | |||
Clock voltage limits | Sine or clipped sine wave, AC coupled | Vpp | 0.7 | 1.2 | Vpp | ||
Phase noise @ 40 MHz | @ 1 kHz | –125 | dBc/Hz | ||||
@ 10 kHz | –138.5 | dBc/Hz | |||||
@ 100 kHz | –143 | dBc/Hz | |||||
Input impedance | Resistance | 12 | KΩ | ||||
Capacitance | 7 | pF |
Table 4-6 lists the RTC crystal requirements.
CHARACTERISTICS | CONDITION | SYM | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
Frequency | 32.768 | kHz | ||||
Frequency accuracy | Initial + temp + aging | ±150 | ppm | |||
Crystal ESR | 32.768 kHz, C1 = C2 = 10 pF | 70 | kΩ |
Table 4-7 lists the external RTC digital clock requirements.
CHARACTERISTICS | CONDITION | SYM | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
Frequency | 32768 | Hz | ||||
Frequency accuracy | ±150 | ppm | ||||
(Initial + temp + aging) | ||||||
Input transition time tr/tf (10% to 90%) | tr/tf | 100 | ns | |||
Frequency input duty cycle | 20 | 50 | 80 | % | ||
Slow clock input voltage limits | Square wave, DC coupled | Vih | 0.65 × VIO | VIO | V | |
Vil | 0 | 0.35 × VIO | V peak | |||
Input impedance | 1 | MΩ | ||||
5 | pF |
Table 4-8 lists the WLAN fast-clock crystal requirements.
CHARACTERISTICS | CONDITION | SYM | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
Frequency | 40 | MHz | ||||
Frequency accuracy | Initial + temp + aging | ±25 | ppm | |||
Crystal ESR | 40 MHz, C1 = C2 = 6.2 pF | 40 | 50 | 60 | Ohm |
The device requires an external bandpass filter to meet the various emission standards, including FCC. Table 4-9 presents the attenuation requirements for the bandpass filter. TI recommends using the same filter used in the reference design to ease the process of certification.
Parameter | Frequency (MHz) | Requirements | |||
---|---|---|---|---|---|
Min | Typ | Max | Units | ||
Return loss | 2412 to 2484 | 10 | dB | ||
Insertion loss(1) | 2412 to 2484 | 1 | 1.5 | dB | |
Attenuation | 800 to 830 | 30 | 45 | dB | |
1600 to 1670 | 20 | 25 | |||
3200 to 3300 | 30 | 48 | |||
4000 to 4150 | 45 | 50 | |||
4800 to 5000 | 20 | 25 | |||
5600 to 5800 | 20 | 25 | |||
6400 to 6600 | 20 | 35 | |||
7200 to 7500 | 35 | 45 | |||
7500 to 10000 | 20 | 25 | |||
Reference Impendence | 2412 to 2484 | 50 | Ω | ||
Filter type | Bandpass |
This section describes the interfaces that are supported by the CC3100 device:
Parameter Number | Parameter(1) | Parameter Name | Min | Max | Unit |
---|---|---|---|---|---|
I1 | F | Clock frequency @ VBAT = 3.3 V | 20 | MHz | |
Clock frequency @ VBAT ≤ 2.1 V | 12 | ||||
I2 | tclk(2) | Clock period | 50 | ns | |
I3 | tLP | Clock low period | 25 | ns | |
I4 | tHT | Clock high period | 25 | ns | |
I5 | D | Duty cycle | 45 | 55 | % |
I6 | tIS | RX data setup time | 4 | ns | |
I7 | tIH | RX data hold time | 4 | ns | |
I8 | tOD | TX data output delay | 20 | ||
I9 | tOH | TX data hold time | 24 | ns |
The external serial flash stores the user profiles and firmware patch updates. The CC3100 device acts as a master in this case; the SPI serial flash acts as the slave device. This interface can work up to a speed of 20 MHz.
Figure 4-15 shows the SPI flash interface.
Table 4-12 lists the SPI flash interface pins.
The device interfaces to an external host using the SPI interface. The CC3100 device can interrupt the host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can work up to a speed of 20 MHz.
Figure 4-16 shows the SPI host interface.
Table 4-13 lists the SPI host interface pins.
Pin Name | Description |
---|---|
HOST_SPI_CLK | Clock (up to 20 MHz) from MCU host to CC3100 device |
HOST_SPI_nCS | CS (active low) signal from MCU host to CC3100 device |
HOST_SPI_MOSI | Data from MCU host to CC3100 device |
HOST_INTR | Interrupt from CC3100 device to MCU host |
HOST_SPI_MISO | Data from CC3100 device to MCU host |
nHIB | Active-low signal that commands the CC3100 device to enter hibernate mode (lowest power state) |
The SimpleLink device requires the UART configuration described in Table 4-14.
Property | Supported CC3100 Configuration |
---|---|
Baud rate | 115200 bps, no auto-baud rate detection, can be changed by the host up to 3 Mbps using a special command |
Data bits | 8 bits |
Flow control | CTS/RTS |
Parity | None |
Stop bits | 1 |
Bit order | LSBit first |
Host interrupt polarity | Active high |
Host interrupt mode | Rising edge or level 1 |
Endianness | Little-endian only(1) |
Figure 4-17 shows the typical 5-wire UART topology comprised of 4 standard UART lines plus one IRQ line from the device to the host controller to allow efficient low power mode.
This is the typical and recommended UART topology because it offers the maximum communication reliability and flexibility between the host and the SimpleLink device.
The 4-wire UART topology eliminates the host IRQ line (see Figure 4-18). Using this topology requires one of the following conditions to be met:
The 3-wire UART topology requires only the following lines (see Figure 4-19):
Using this topology requires one of the following conditions to be met:
Because there is no full flow control, the host cannot stop the SimpleLink device to send its data; thus, the following parameters must be carefully considered:
Figure 5-1 shows the functional block diagram of the CC3100 SimpleLink Wi-Fi solution.
The Wi-Fi network processor subsystem includes a dedicated ARM MCU to completely offload the host MCU along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN and Internet connections with 256-bit encryption. The CC3100 device supports station, AP, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi network processor includes an embedded IPv4 TCP/IP stack.
Table 5-1 summarizes the NWP features.
Item | Domain | Category | Feature | Details |
---|---|---|---|---|
1 | TCP/IP | Network Stack | IPv4 | Baseline IPv4 stack |
2 | TCP/IP | Network Stack | TCP/UDP | Base protocols |
3 | TCP/IP | Protocols | DHCP | Client and server mode |
4 | TCP/IP | Protocols | ARP | Support ARP protocol |
5 | TCP/IP | Protocols | DNS/mDNS | DNS Address resolution and local server |
6 | TCP/IP | Protocols | IGMP | Up to IGMPv3 for multicast management |
7 | TCP/IP | Applications | mDNS | Support multicast DNS for service publishing over IP |
8 | TCP/IP | Applications | mDNS-SD | Service discovery protocol over IP in local network |
9 | TCP/IP | Applications | Web Sever/HTTP Server | URL static and dynamic response with template. |
10 | TCP/IP | Security | TLS/SSL | TLS v1.2 (client/server)/SSL v3.0 |
11 | TCP/IP | Security | TLS/SSL | For the supported Cipher Suite, go to SimpleLink Wi-Fi CC3100 SDK. |
12 | TCP/IP | Sockets | RAW Sockets | User-defined encapsulation at WLAN MAC/PHY or IP layers |
13 | WLAN | Connection | Policies | Allows management of connection and reconnection policy |
14 | WLAN | MAC | Promiscuous mode | Filter-based Promiscuous mode frame receiver |
15 | WLAN | Performance | Initialization time | From enable to first connection to open AP less than 50 ms |
16 | WLAN | Performance | Throughput | UDP = 16 Mbps |
17 | WLAN | Performance | Throughput | TCP = 13 Mbps |
18 | WLAN | Provisioning | WPS2 | Enrollee using push button or PIN method. |
19 | WLAN | Provisioning | AP Config | AP mode for initial product configuration (with configurable Web page and beacon Info element) |
20 | WLAN | Provisioning | SmartConfig | Alternate method for initial product configuration |
21 | WLAN | Role | Station | 802.11bgn Station with legacy 802.11 power save |
22 | WLAN | Role | Soft AP | 802.11 bg single station with legacy 802.11 power save |
23 | WLAN | Role | P2P | P2P operation as GO |
24 | WLAN | Role | P2P | P2P operation as CLIENT |
25 | WLAN | Security | STA-Personal | WPA2 personal security |
26 | WLAN | Security | STA-Enterprise | WPA2 enterprise security |
27 | WLAN | Security | STA-Enterprise | EAP-TLS |
28 | WLAN | Security | STA-Enterprise | EAP-PEAPv0/TLS |
29 | WLAN | Security | STA-Enterprise | EAP-PEAPv1/TLS |
30 | WLAN | Security | STA-Enterprise | EAP-PEAPv0/MSCHAPv2 |
31 | WLAN | Security | STA-Enterprise | EAP-PEAPv1/MSCHAPv2 |
32 | WLAN | Security | STA-Enterprise | EAP-TTLS/EAP-TLS |
33 | WLAN | Security | STA-Enterprise | EAP-TTLS/MSCHAPv2 |
34 | WLAN | Security | AP-Personal | WPA2 personal security |
The CC3100 power-management subsystem contains DC-DC converters to accommodate the differing voltage or current requirements of the system.
In preregulated 1.85-V mode, the ANA1 DC-DC and PA DC-DC converters are bypassed. The CC3100 device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage supply range. The internal power management, including DC-DC converters and LDOs, generates all of the voltages required for the device to operate from a wide variety of input sources. For maximum flexibility, the device can operate in the modes described in the following sections.
In the wide-voltage battery connection, the device is powered directly by the battery. All other voltages required to operate the device are generated internally by the DC-DC converters. This scheme is the most common mode for the device as it supports wide-voltage operation from 2.1 to 3.6 V (for electrical connections, see Section 6.1.1, Typical Application – CC3100 Wide-Voltage Mode).
The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at the pins 10, 25, 33, 36, 37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V supply. This mode provides the lowest BOM count version in which inductors used for PA DC-DC and ANA1 DC-DC (2.2 and 1 µH) and a capacitor (22 µF) can be avoided. For electrical connections, see Section 6.1.2, Typical Application – CC3100 Preregulated 1.85-V Mode.
In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following characteristics:
This section describes the low-power modes supported by the device to optimize battery life.
The low-power deep-sleep (LPDS) mode is an energy-efficient and transparent sleep mode that is entered automatically during periods of inactivity based on internal power optimization algorithms. The device can wake up in less than 3 ms from the internal timer or from any incoming host command. Typical battery drain in this mode is 115 µA. During LPDS mode, the device retains the software state and certain configuration information. The operation is transparent to the external host; thus, no additional handshake is required to enter or exit this sleep mode.
The hibernate mode is the lowest power mode in which all of the digital logic is power-gated. Only a small section of the logic powered directly by the main input supply is retained. The real-time clock (RTC) is kept running and the device wakes up once the nHIB line is asserted by the host driver. The wake-up time is longer than LPDS mode at about 50 ms.
NOTE
Wake-up time can be extended to 75 ms if a patch is loaded from the serial flash.
The CC3100 device maintains a proprietary file system on the SFLASH. The CC3100 file system stores the service pack file, system files, configuration files, certificate files, web page files, and user files. By using a format command through the API, users can provide the total size allocated for the file system. The starting address of the file system cannot be set and is always located at the beginning of the SFLASH. The applications microcontroller must access the SFLASH memory area allocated to the file system directly through the CC3100 file system. The applications microcontroller must not access the SFLASH memory area directly.
The file system manages the allocation of SFLASH blocks for stored files according to download order, which means that the location of a specific file is not fixed in all systems. Files are stored on SFLASH using human-readable file names rather than file IDs. The file system API works using plain text, and file encryption and decryption is invisible to the user. Encrypted files can be accessed only through the file system.
All file types can have a maximum of 128 supported files in the file system. All files are stored in blocks of 4KB and thus use a minimum of 4KB of flash space. Encrypted files with fail-safe support and optional security are twice the original size and use a minimum of 8KB. Encrypted files are counted as fail safe in terms of space. The maximum file size is 16MB.
Table 5-2 lists the SFLASH size recommendations.
Item | Typical Fail-Safe | Typical NonFail-Safe |
---|---|---|
File system | 20KB | 20KB |
Service pack | 224KB | 112KB |
System and configuration files | 216KB | 108KB |
Total | 4Mb | 2Mb |
Recommended | 8Mb | 4Mb |
The CC3100 device supports JEDEC specification SFDP (serial flash device parameters). The following SFLASH devices are verified for functionality with the CC3100 device in addition to the ones in the reference design:
For compatibility with the CC3100 device, the SFLASH device must support the following commands:
Figure 6-1 shows the schematics for an application using the CC3100 wide-voltage mode.
Table 6-1 lists the bill of materials for an application using the CC3100 wide-voltage mode.
Item | Qty | Reference | Value | Manufacturer | Part Number | Description |
---|---|---|---|---|---|---|
1 | 12 | C1 C5 C6 C9 C10 C11 C12 C17 C18 C20 C21 C28 | 0.1 µF | Taiyo Yuden | LMK105BJ104KV-F | CAP CER 0.1 µF 10 V 10% X5R 0402 |
2 | 3 | C2 C3 C4 | 4.7 µF | Samsung Electro-Mechanics America, Inc | CL05A475MQ5NRNC | CAP CER 4.7 µF 6.3 V 20% X5R 0402 |
3 | 1 | C8 | 1.0 pF | Murata Electronics North America | GJM1555C1H1R0BB01D | CAP CER 1 pF 50 V NP0 0402 |
4 | 1 | C13 | 22 µF | Taiyo Yuden | AMK107BBJ226MAHT | CAP CER 22 µF 4 V 20% X5R 0603 |
5 | 1 | C16 | 10 µF | Murata Electronics North America | GRM188R60J106ME47D | CAP CER 10 µF 6.3 V 20% X5R 0603 |
6 | 2 | C22 C23 | 10 pF | Murata Electronics North America | GRM1555C1H100FA01D | CAP CER 10 pF 50 V 1% NP0 0402 |
7 | 2 | C24 C25 | 6.2 pF | Kemet | CBR04C609B1GAC | CAP CER 6 pF 100 V NP0 0402 |
8 | 2 | C26 C27 | 100 µF | TDK Corportation | C3216X5R0J107M160AB | CAP CER 100 µF 6.3 V 20% X5R 1206 |
9 | 1 | E1 | 2.45G Hz Ant | Taiyo Yuden | AH316M245001-T | ANT BLUETOOTH WLAN ZIGBEE WIMAX |
10 | 1 | FL1 | 2.4G Hz Filter | TDK-Epcos | DEA202450BT-1294C1-H | FILTER BANDPASS 2.45 GHZ WLAN SMD |
11 | 1 | L2 | 3.6 nH | Murata Electronics North America | LQP15MN3N6B02D | INDUCTOR 3.6 nH 0.1 nH 0402 |
12 | 1 | L4 | 2.2 µH | Murata Electronics North America | LQM2HPN2R2MG0L | INDUCTOR 2.2 µH 20% 1300 mA 1008 |
13 | 1 | U1 | CC3100 | Texas Instruments | CC3100R1 | 802.11bg Wi-Fi Processor |
14 | 1 | U2 | 8M (1M x 8) | Winbond | W25Q80BWZPIG | IC FLASH 8 Mb 75 MHZ 8WSON |
15 | 1 | Y1 | Crystal | Abracon Corporation | ABS07-32.768KHZ-T | CRYSTAL 32.768 KHZ 12.5 pF SMD |
16 | 1 | Y2 | Crystal | Epson | Q24FA20H00396 | CRYSTAL 40 MHZ 8 pF SMD |
NOTE
Use any 5% tolerance resistor 0402 or higher package.
Figure 6-2 shows the schematics for an application using the CC3100 preregulated 1.85-V mode.
Table 6-1 lists the bill of materials for an application using the CC3100 preregulated 1.85-V mode.
Item | Qty | Reference | Value | Manufacturer | Part Number | Description |
---|---|---|---|---|---|---|
1 | 12 | C1 C5 C6 C9 C10 C11 C12 C17 C18 C20 C21 C28 | 0.1 µF | Taiyo Yuden | LMK105BJ104KV-F | Capacitor, Ceramic: 0.1 µF 10 V 10% X5R 0402 |
2 | 4 | C2 C3 C4 C7 | 4.7 µF | Samsung Electro-Mechanics America, Inc | CL05A475MQ5NRNC | Capacitor, Ceramic: 4.7 µF 6.3 V 20% X5R 0402 |
3 | 1 | C8 | 1.0 pF | Murata Electronics North America | GJM1555C1H1R0BB01D | Capacitor, Ceramic: 1 pF 50 V NP0 0402 |
4 | 1 | C13 | 22 µF | Taiyo Yuden | AMK107BBJ226MAHT | Capacitor, Ceramic: 22 µF 4 V 20% X5R 0603 |
5 | 1 | C16 | 10 µF | Murata Electronics North America | GRM188R60J106ME47D | Capacitor, Ceramic: 10 µF 6.3 V 20% X5R 0603 |
6 | 2 | C22 C23 | 10 pF | Murata Electronics North America | GRM1555C1H100FA01D | Capacitor, Ceramic: 10 pF 50 V 1% NP0 0402 |
7 | 2 | C24 C25 | 6.2 pF | Kemet | CBR04C609B1GAC | Capacitor, Ceramic: 6 pF 100 V NP0 0402 |
8 | 2 | C26 C27 | 100 µF | TDK Corportation | C3216X5R0J107M160AB | Capacitor, Ceramic: 100 µF 6.3 V 20% X5R 1206 |
9 | 1 | E1 | 2.45-GHz Ant | Taiyo Yuden | AH316M245001-T | Antenna, Bluetooth: WLAN ZigBee WIMAX |
10 | 1 | FL1 | 2.4-GHz Filter | TDK-Epcos | DEA202450BT-1294C1-H | Filter, Bandpass: 2.45 GHz WLAN SMD |
11 | 1 | L2 | 3.6 nH | Murata Electronics North America | LQP15MN3N6B02D | Inductor: 3.6 nH 0.1 nH 0402 |
12 | 1 | L4 | 2.2 µH | Murata Electronics North America | LQM2HPN2R2MG0L | Inductor: 2.2 µH 20% 1300 mA 1008 |
13 | 1 | U1 | CC3100 | Texas Instruments | CC3100R1 | 802.11bg Wi-Fi Processor |
14 | 1 | U2 | 8M (1M x 8) |
Winbond | W25Q80BWZPIG | IC Flash 8 Mb 75 MHz 8WSON |
15 | 1 | Y1 | Crystal | Abracon Corporation | ABS07-32.768KHZ-T | Crystal 32.768 kHz 12.5 pF SMD |
16 | 1 | Y2 | Crystal | Epson | Q24FA20H00396 | Crystal 40 MHZ 8 pF SMD |
NOTE
Use any 5% tolerance resistor 0402 or higher package.