SWRS227C March   2020  – December 2024 CC3130

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1.      12
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Current Consumption Summary
    6. 7.6  TX Power Control
    7. 7.7  Brownout and Blackout Conditions
      1. 7.7.1 Brownout and Blackout Voltage Levels
    8. 7.8  Electrical Characteristics for DIO Pins
      1. 7.8.1 Electrical Characteristics: DIO Pins Except 52 and 53
      2. 7.8.2 Electrical Characteristics: DIO Pins 52 and 53
    9. 7.9  Electrical Characteristics for Pin Internal Pullup and Pulldown
    10. 7.10 WLAN Receiver Characteristics
      1.      28
    11. 7.11 WLAN Transmitter Characteristics
      1.      30
    12. 7.12 WLAN Transmitter Out-of-Band Emissions
      1. 7.12.1 WLAN 2.4GHz Filter Requirements
    13. 7.13 BLE/2.4GHz Radio Coexistence and WLAN Coexistence Requirements
    14. 7.14 Thermal Resistance Characteristics for RGK Package
    15. 7.15 Timing and Switching Characteristics
      1. 7.15.1 Power Supply Sequencing
      2. 7.15.2 Device Reset
      3. 7.15.3 Reset Timing
        1. 7.15.3.1 nRESET (32-kHz Crystal)
        2. 7.15.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32kHz Crystal)
        3. 7.15.3.3 nRESET (External 32kHz Crystal)
          1. 7.15.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32kHz Crystal)
      4. 7.15.4 Wakeup from HIBERNATE Mode
        1. 7.15.4.1 nHIB Timing Requirements
      5. 7.15.5 Clock Specifications
        1. 7.15.5.1 Slow Clock Using Internal Oscillator
          1. 7.15.5.1.1 RTC Crystal Requirements
        2. 7.15.5.2 Slow Clock Using an External Clock
          1. 7.15.5.2.1 External RTC Digital Clock Requirements
        3. 7.15.5.3 Fast Clock (Fref) Using an External Crystal
          1. 7.15.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 7.15.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 7.15.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 7.15.6 Interfaces
        1. 7.15.6.1 Host SPI Interface Timing
          1. 7.15.6.1.1 Host SPI Interface Timing Parameters
        2. 7.15.6.2 Flash SPI Interface Timing
          1. 7.15.6.2.1 Flash SPI Interface Timing Parameters
        3. 7.15.6.3 DIO Interface Timing
          1. 7.15.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3V)
            1. 7.15.6.3.1.1 DIO Output Transition Times (Vsupply = 3.3V) #GUID-01C4FDBB-69B0-4F3E-AD14-CDACB1CFA3A4/SWAS03298470_
          2. 7.15.6.3.2 DIO Input Transition Time Parameters
            1. 7.15.6.3.2.1 DIO Input Transition Time Parameters
    16. 7.16 External Interfaces
      1. 7.16.1 SPI Flash Interface
      2. 7.16.2 SPI Host Interface
      3. 7.16.3 Host UART Interface
        1. 7.16.3.1 5-Wire UART Topology
        2. 7.16.3.2 4-Wire UART Topology
        3. 7.16.3.3 3-Wire UART Topology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Device Features
      1. 8.2.1 WLAN
      2. 8.2.2 Network Stack
      3. 8.2.3 Security
      4. 8.2.4 Host Interface and Driver
      5. 8.2.5 System
    3. 8.3 Power-Management Subsystem
      1. 8.3.1 VBAT Wide-Voltage Connection
    4. 8.4 Low-Power Operating Modes
      1. 8.4.1 Low-Power Deep Sleep
      2. 8.4.2 Hibernate
      3. 8.4.3 Shutdown
    5. 8.5 Memory
      1. 8.5.1 External Memory Requirements
    6. 8.6 Restoring Factory Default Configuration
    7. 8.7 Hostless Mode
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
      1. 9.1.1 BLE/2.4GHz Radio Coexistence
      2. 9.1.2 Antenna Selection
      3. 9.1.3 Typical Application
    2. 9.2 PCB Layout Guidelines
      1. 9.2.1 General PCB Guidelines
      2. 9.2.2 Power Layout and Routing
        1. 9.2.2.1 Design Considerations
      3. 9.2.3 Clock Interface Guidelines
      4. 9.2.4 Digital Input and Output Guidelines
      5. 9.2.5 RF Interface Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Tools and Software
    2. 10.2 Firmware Updates
    3. 10.3 Device Nomenclature
    4. 10.4 Documentation Support
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 6-2 Signal Descriptions
FUNCTIONSIGNAL NAMEPIN
NO.		PIN
TYPE		SIGNAL DIRECTIONDESCRIPTION
Antenna selectionDIO101I/OOAntenna selection control
DIO123I/OO
DIO134I/OO
DIO2316I/OO
DIO2417I/OO
DIO2818(1)I/OO
DIO2920I/OO
DIO2521OO
DIO3145(1)I/OO
DIO3252(1)I/OO
DIO3053(1)I/OO
DIO358I/OO
DIO459I/OO
DIO560I/OO
DIO863I/OO
DIO964I/OO

ANTSEL1

29

O

O

Antenna selection control 1

ANTSEL2

30

O

O

Antenna selection control 2

BLE/2.4 GHz Radio coexistenceDIO101I/OI/OCoexistence inputs and outputs
DIO123I/OI/O
DIO134I/OI/O
DIO2316I/OI/O
DIO2417I/OI/O
DIO2818(1)I/OI/O
DIO2920I/OI/O
DIO2521OO
DIO3145(1)I/OI/O
DIO3252(1)I/OI/O
DIO3053(1)I/OI/O
DIO358I/OI/O
DIO459I/OI/O
DIO560I/OI/O
DIO863I/OI/O
DIO964I/OI/O
ClockWLAN_XTAL_N22——40MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P23——40MHz crystal or TCXO clock input
RTC_XTAL_P51——Connect 32.768kHz crystal or force external CMOS level clock
RTC_XTAL_N52——Connect 32.768kHz crystal or connect 100kΩ resistor to supply voltage
Hostless ModeDIO101I/OI/OHostless mode inputs and outputs
DIO123I/OI/O
DIO134I/OI/O
DIO2316I/OI/O
DIO2417I/OI/O
DIO2818(1)I/OI/O
DIO2920I/OI/O
DIO2521OO
DIO3145(1)I/OI/O
DIO3252(1)I/OI/O
DIO3053(1)I/OI/O
DIO358I/OI/O
DIO459I/OI/O
DIO560I/OI/O
DIO863I/OI/O
DIO964I/OI/O
PowerVDD_DIG19——Internal digital core voltage
VIN_IO110——Device supply voltage (VBAT)
VDD_PLL24——Internal analog voltage
LDO_IN225——Internal analog RF supply from analog DC/DC output
VDD_PA_IN33——Internal PA supply voltage from PA DC/DC output
LDO_IN136——Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA37——Analog DC/DC input (connected to device input supply [VBAT])
DCDC_ANA_SW38——Internal analog DC/DC switching node
VIN_DCDC_PA39——PA DC/DC input (connected to device input supply [VBAT])
DCDC_PA_SW_P40——Internal PA DC/DC switching node
DCDC_PA_SW_N41——Internal PA DC/DC switching node
DCDC_PA_OUT42——Internal PA buck converter output
DCDC_DIG_SW43——Internal digital DC/DC switching node
VIN_DCDC_DIG44——Digital DC/DC input (connected to device input supply [VBAT])
DCDC_ANA2_SW_P45——Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N46——Internal analog to DC/DC converter –ve switching node
VDD_ANA247——Internal analog to DC/DC output
VDD_ANA148——Internal analog supply fed by ANA2 DC/DC output
VDD_RAM49——Internal SRAM LDO output
VIN_IO254——Device supply voltage (VBAT)
VDD_DIG256——Internal digital core voltage
HOST SPIHOST_SPI_CLK5I/OIHost SPI clock input
HOST_SPI_MOSI6I/OIData from Host
HOST_SPI_MISO8I/OOData to Host
HOST_SPI_nCS7I/OIDevice select (active low)
FLASH SPIFLASH_SPI_CLK11OOClock to SPI serial flash (fixed default)
FLASH_SPI_DOUT12OOData to SPI serial flash (fixed default)
FLASH_SPI_DIN13IIData from SPI serial flash (fixed default)
FLASH_SPI_CS14OODevice select to SPI serial flash (fixed default)
UARTUART1_nRTS50I/OOUART1 request-to-send (active low)
UART1_TX55I/OIUART TX data
UART1_RX57I/OOUART RX data
UART1_nCTS61I/OIUART1 clear-to-send (active low)
Sense-On-PowerSOP221(2)OISense-on-power 2
SOP134IIConfiguration sense-on-power 1
SOP035IIConfiguration sense-on-power 0
ResetnRESET32IIGlobal master device reset (active low)
nHIBnHIB2IIHibernate signal input to the NWP subsystem (active low)
RFRF_BG31I/OI/OWLAN analog RF 802.11b/g/n bands
Test PortTEST_5858OOTest Signal
TEST_5959IITest Signal
TEST_6060OOTest Signal
TEST_6262OOTest Signal
(1) LPDS retention is unavailable.
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.