SWRS206E March   2017  – May 2021 CC3220MOD , CC3220MODA

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3220MODx and CC3220MODAx Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Module Pin Attributes
    3. 7.3 Connections for Unused Pins
    4. 7.4 Pin Attributes and Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip, but Before Reset Release
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption (CC3220MODS and CC3220MODAS)
    5. 8.5  Current Consumption (CC3220MODSF and CC3220MODASF)
    6. 8.6  TX Power and IBAT Versus TX Power Level Settings
    7. 8.7  Brownout and Blackout Conditions
    8. 8.8  Electrical Characteristics
    9. 8.9  CC3220MODAx Antenna Characteristics
    10. 8.10 WLAN Receiver Characteristics
    11. 8.11 WLAN Transmitter Characteristics
    12. 8.12 Reset Requirement
    13. 8.13 Thermal Resistance Characteristics for MOB and MON Packages
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power-Up Sequencing
      2. 8.14.2 Power-Down Sequencing
      3. 8.14.3 Device Reset
      4. 8.14.4 Wake Up From Hibernate Timing
      5. 8.14.5 Peripherals Timing
        1. 8.14.5.1  SPI
          1. 8.14.5.1.1 SPI Master
          2. 8.14.5.1.2 SPI Slave
        2. 8.14.5.2  I2S
          1. 8.14.5.2.1 I2S Transmit Mode
          2. 8.14.5.2.2 I2S Receive Mode
        3. 8.14.5.3  GPIOs
          1. 8.14.5.3.1 GPIO Input Transition Time Parameters
        4. 8.14.5.4  I2C
        5. 8.14.5.5  IEEE 1149.1 JTAG
        6. 8.14.5.6  ADC
        7. 8.14.5.7  Camera Parallel Port
        8. 8.14.5.8  UART
        9. 8.14.5.9  External Flash Interface
        10. 8.14.5.10 SD Host
        11. 8.14.5.11 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  Power-Management Subsystem
      1. 9.5.1 VBAT Wide-Voltage Connection
    6. 9.6  Low-Power Operating Mode
    7. 9.7  Memory
      1. 9.7.1 Internal Memory
        1. 9.7.1.1 SRAM
        2. 9.7.1.2 ROM
        3. 9.7.1.3 Flash Memory
        4. 9.7.1.4 Memory Map
    8. 9.8  Restoring Factory Default Configuration
    9. 9.9  Boot Modes
      1. 9.9.1 Boot Mode List
    10. 9.10 Device Certification and Qualification
      1. 9.10.1 FCC Certification and Statement
      2. 9.10.2 Industry Canada (IC) Certification and Statement
      3. 9.10.3 ETSI/CE Certification
      4. 9.10.4 MIC Certification
      5. 9.10.5 SRRC Certification and Statement
    11. 9.11 Module Markings
    12. 9.12 End Product Labeling
    13. 9.13 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Typical Application
    2. 10.2 Device Connection and Layout Fundamentals
      1. 10.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.2.2 Reset
      3. 10.2.3 Unused Pins
    3. 10.3 PCB Layout Guidelines
      1. 10.3.1 General Layout Recommendations
      2. 10.3.2 CC3220MODx RF Layout Recommendations
        1. 10.3.2.1 Antenna Placement and Routing
        2. 10.3.2.2 Transmission Line Considerations
      3. 10.3.3 CC3220MODAx RF Layout Recommendations
  11. 11Environmental Requirements and Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Development Tools and Software
    2. 12.2 Firmware Updates
    3. 12.3 Device Nomenclature
    4. 12.4 Documentation Support
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
        1. 13.2.2.1 CC3220MODx Tape Specifications
        2. 13.2.2.2 CC3220MODAx Tape Specifications

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MOB|63
Thermal pad, mechanical data (Package|Pins)

8.14.5.10 SD Host

The CC3220MODx and CC3220MODAx modules provide an interface between a local host (LH), such as an MCU and an SD memory card, and handles SD transactions with minimal LH intervention.

The SD host does the following:

  • Provides SD card access in 1-bit mode
  • Deals with SD protocol at the transmission level
  • Handles data packing
  • Adds cyclic redundancy checks (CRC)
  • Start and end bit
  • Checks for syntactical correctness

The application interface sends every SD command and either polls for the status of the adapter or waits for an interrupt request. The result is then sent back to the application interface in case of exceptions or to warn of end-of-operation. The controller can be configured to generate DMA requests and work with minimum CPU intervention. Given the nature of integration of this peripheral on the CC3220x platform, TI recommends that developers use peripheral library APIs to control and operate the block. This section emphasizes understanding the SD host APIs provided in the peripheral library of the CC3220x Software Development Kit (SDK).

The SD Host features are as follows:

  • Full compliance with SD command and response sets, as defined in the SD memory card
    • Specifications, v2.0
    • Includes high-capacity (size >2 GB) cards HC SD
  • Flexible architecture, allowing support for new command structure.
  • 1-bit transfer mode specifications for SD cards
  • Built-in 1024-byte buffer for read or write
    • 512-byte buffer for both transmit and receive
    • Each buffer is 32-bits wide by 128-words deep
  • 32-bit-wide access bus to maximize bus throughput
  • Single interrupt line for multiple interrupt source events
  • Two slave DMA channels (1 for TX, 1 for RX)
  • Programmable clock generation
  • Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver
  • Supports configurable busy and response timeout
  • Support for a wide range of card clock frequency with odd and even clock ratio
  • Maximum frequency supported is 24 MHz