SWAS035C September   2016  – May 2021 CC3220R , CC3220S , CC3220SF

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagrams
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes and Pin Multiplexing
      1. 7.2.1 Pin Descriptions
    3. 7.3 Signal Descriptions
      1. 7.3.1 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip But Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3220R, CC3220S)
    6. 8.6  Current Consumption Summary (CC3220SF)
    7. 8.7  TX Power and IBAT versus TX Power Level Settings
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics (3.3 V, 25°C)
    10. 8.10 WLAN Receiver Characteristics
    11. 8.11 WLAN Transmitter Characteristics
    12. 8.12 WLAN Filter Requirements
      1. 8.12.1 WLAN Filter Requirements
    13. 8.13 Thermal Resistance Characteristics
      1. 8.13.1 Thermal Resistance Characteristics for RGK Package
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power Supply Sequencing
      2. 8.14.2 Device Reset
      3. 8.14.3 Reset Timing
        1. 8.14.3.1 nRESET (32-kHz Crystal)
        2. 8.14.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. 8.14.3.3 nRESET (External 32-kHz)
          1. 8.14.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz)
      4. 8.14.4 Wakeup From HIBERNATE Mode
      5. 8.14.5 Clock Specifications
        1. 8.14.5.1 Slow Clock Using Internal Oscillator
          1. 8.14.5.1.1 RTC Crystal Requirements
        2. 8.14.5.2 Slow Clock Using an External Clock
          1. 8.14.5.2.1 External RTC Digital Clock Requirements
        3. 8.14.5.3 Fast Clock (Fref) Using an External Crystal
          1. 8.14.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 8.14.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 8.14.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 8.14.6 Peripherals Timing
        1. 8.14.6.1  SPI
          1. 8.14.6.1.1 SPI Master
            1. 8.14.6.1.1.1 SPI Master Timing Parameters
          2. 8.14.6.1.2 SPI Slave
            1. 8.14.6.1.2.1 SPI Slave Timing Parameters
        2. 8.14.6.2  I2S
          1. 8.14.6.2.1 I2S Transmit Mode
            1. 8.14.6.2.1.1 I2S Transmit Mode Timing Parameters
          2. 8.14.6.2.2 I2S Receive Mode
            1. 8.14.6.2.2.1 I2S Receive Mode Timing Parameters
        3. 8.14.6.3  GPIOs
          1. 8.14.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1. 8.14.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V) (1) (1)
          2. 8.14.6.3.2 GPIO Output Transition Time Parameters (Vsupply = 1.85 V)
            1. 8.14.6.3.2.1 GPIO Output Transition Times (Vsupply = 1.85 V) (1) (1)
          3. 8.14.6.3.3 GPIO Input Transition Time Parameters
            1. 8.14.6.3.3.1 GPIO Input Transition Time Parameters'
        4. 8.14.6.4  I2C
          1. 8.14.6.4.1 I2C Timing Parameters (1)
        5. 8.14.6.5  IEEE 1149.1 JTAG
          1. 8.14.6.5.1 JTAG Timing Parameters
        6. 8.14.6.6  ADC
          1. 8.14.6.6.1 ADC Electrical Specifications
        7. 8.14.6.7  Camera Parallel Port
          1. 8.14.6.7.1 Camera Parallel Port Timing Parameters
        8. 8.14.6.8  UART
        9. 8.14.6.9  SD Host
        10. 8.14.6.10 Timers
  9. Detailed Description
    1. 9.1 Arm® Cortex®-M4 Processor Core Subsystem
    2. 9.2 Wi-Fi Network Processor Subsystem
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
    3. 9.3 Security
    4. 9.4 Power-Management Subsystem
      1. 9.4.1 VBAT Wide-Voltage Connection
      2. 9.4.2 Preregulated 1.85-V Connection
    5. 9.5 Low-Power Operating Mode
    6. 9.6 Memory
      1. 9.6.1 External Memory Requirements
      2. 9.6.2 Internal Memory
        1. 9.6.2.1 SRAM
        2. 9.6.2.2 ROM
        3. 9.6.2.3 Flash Memory
        4. 9.6.2.4 Memory Map
    7. 9.7 Restoring Factory Default Configuration
    8. 9.8 Boot Modes
      1. 9.8.1 Boot Mode List
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application —CC3220x Wide-Voltage Mode
      2. 10.1.2 Typical Application Schematic—CC3220x Preregulated, 1.85-V Mode
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interfaces
      4. 10.2.4 Digital Input and Output
      5. 10.2.5 RF Interface
  11. 11Device and Documentation Support
    1. 11.1 Development Tools and Software
    2. 11.2 Firmware Updates
    3. 11.3 Device Nomenclature
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Multiplexing

Table 7-2 Pin Multiplexing
REGISTER ADDRESS REGISTER NAME PIN ANALOG OR SPECIAL FUNCTION DIGITAL FUNCTION (XXX FIELD ENCODING)(1)
JTAG 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x4402 E0C8 GPIO_PAD_CONFIG_10 1 GPIO10 I2C_SCL GT_PWM06 SDCARD_CLK UART1_TX GT_CCP01
0x4402 E0CC GPIO_PAD_CONFIG_11 2 GPIO11 I2C_SDA GT_PWM07 pXCLK (XVCLK) SDCARD_CMD UART1_RX GT_CCP02 MCAFSX
0x4402 E0D0 GPIO_PAD_CONFIG_12 3 GPIO12 McACLK pVS (VSYNC) I2C_SCL UART0_TX GT_CCP03
0x4402 E0D4 GPIO_PAD_CONFIG_13 4 GPIO13 pHS (HSYNC) I2C_SDA UART0_RX GT_CCP04
0x4402 E0D8 GPIO_PAD_CONFIG_14 5 GPIO14 pDATA8 (CAM_D4) I2C_SCL GSPI_CLK GT_CCP05
0x4402 E0DC GPIO_PAD_CONFIG_15 6 GPIO15 pDATA9 (CAM_D5) I2C_SDA GSPI_
MISO
SDCARD_DATA0 GT_CCP06
0x4402 E0E0 GPIO_PAD_CONFIG_16 7 GPIO16 pDATA10 (CAM_D6) UART1_TX GSPI_
MOSI
SDCARD_CLK GT_CCP07
0x4402 E0E4 GPIO_PAD_CONFIG_17 8 GPIO17 pDATA11 (CAM_D7) UART1_RX GSPI_CS SDCARD_CMD
0x4402 E0F8 GPIO_PAD_CONFIG_22 15 GPIO22 GT_CCP04 McAFSX
0x4402 E0FC GPIO_PAD_CONFIG_23 16 Muxed with JTAG GPIO23 TDI UART1_TX I2C_SCL
0x4402 E100 GPIO_PAD_CONFIG_24 17 Muxed with JTAG TDO GPIO24 TDO UART1_RX GT_CCP06 PWM0 McAFSX I2C_SDA
0x4402 E140 GPIO_PAD_CONFIG_40 18 GPIO28
0x4402 E110 GPIO_PAD_CONFIG_28 19 Muxed with JTAG or SWD and TCK TCK GT_
PWM03
0x4402 E114 GPIO_PAD_CONFIG_29 20 Muxed with JTAG or SWD and TMSC GPIO29 TMS
0x4402 E104 GPIO_PAD_CONFIG_25 21(2) GPIO25 McAFSX GT_
PWM02
0x4402 E108 GPIO_PAD_CONFIG_26 29 ANTSEL1(3)
0x4402 E10C GPIO_PAD_CONFIG_27 30 ANTSEL2(3)
0x4402 E11C GPIO_PAD_CONFIG_31 45 GPIO31 UART1_RX McAXR0 GSPI_CLK UART0_RX McAFSX
0x4402 E0A0 GPIO_PAD_CONFIG_0 50 GPIO0 UART0_
RTS
McAXR0 McAXR1 GT_CCP00 GSPI_CS UART1_
RTS
UART0_
CTS
0x4402 E120 GPIO_PAD_CONFIG_32 52 GPIO32 McACLK McAXR0 UART0 _
RTS
GSPI_
MOSI
0x4402 E118 GPIO_PAD_CONFIG_30 53 -— GPIO30 McACLK McAFSX GT_CCP05 GSPI_
MISO
UART0_TX
0x4402 E0A4 GPIO_PAD_CONFIG_1 55 GPIO1 UART0_TX pCLK (PIXCLK) UART1_TX GT_CCP01
0x4402 E0A8 GPIO_PAD_CONFIG_2 57 GPIO2 UART0_RX UART1_RX GT_CCP02
0x4402 E0AC GPIO_PAD_CONFIG_3 58 GPIO3 pDATA7 (CAM_D3) UART1_TX
0x4402 E0B0 GPIO_PAD_CONFIG_4 59 GPIO4 pDATA6 (CAM_D2) UART1_RX
0x4402 E0B4 GPIO_PAD_CONFIG_5 60 GPIO5 pDATA5 (CAM_D1) McAXR1 GT_CCP05
0x4402 E0B8 GPIO_PAD_CONFIG_6 61 GPIO6 UART1_
CTS
pDATA4 (CAM_D0) UART0_
RTS
UART0_
CTS
GT_CCP06
0x4402 E0BC GPIO_PAD_CONFIG_7 62 GPIO7 UART1_
RTS
UART0_
RTS
UART0_TX McACLKX
0x4402 E0C0 GPIO_PAD_CONFIG_8 63 GPIO8 SDCARD_
IRQ
McAFSX GT_CCP06
0x4402 E0C4 GPIO_PAD_CONFIG_9 64 -— GPIO9 GT_PWM05 SDCARD_
DATA0
McAXR0 GT_CCP00
Pin mux encodings with (RD) denote the default encoding after reset release.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.