SWRS226B February   2020  – May 2021 CC3230S , CC3230SF

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Pin Descriptions
    3. 7.3 Signal Descriptions
      1.      13
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Device, Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3230S)
      1.      24
    6. 8.6  Current Consumption Summary (CC3230SF)
      1.      26
    7. 8.7  TX Power Control
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics for GPIO Pins
      1. 8.9.1 Electrical Characteristics: GPIO Pins Except 29, 30, 50, 52, and 53
      2. 8.9.2 Electrical Characteristics: GPIO Pins 29, 30, 50, 52, and 53
    10. 8.10 Electrical Characteristics for Pin Internal Pullup and Pulldown
      1.      33
    11. 8.11 WLAN Receiver Characteristics
      1.      35
    12. 8.12 WLAN Transmitter Characteristics
      1.      37
    13. 8.13 WLAN Transmitter Out-of-Band Emissions
      1. 8.13.1 WLAN Filter Requirements
    14. 8.14 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    15. 8.15 Thermal Resistance Characteristics for RGK Package
    16. 8.16 Timing and Switching Characteristics
      1. 8.16.1 Power Supply Sequencing
      2. 8.16.2 Device Reset
      3. 8.16.3 Reset Timing
        1. 8.16.3.1 nRESET (32-kHz Crystal)
        2. 8.16.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. 8.16.3.3 nRESET (External 32-kHz Clock)
          1. 8.16.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Clock)
      4. 8.16.4 Wakeup From HIBERNATE Mode
      5. 8.16.5 Clock Specifications
        1. 8.16.5.1 Slow Clock Using Internal Oscillator
        2. 8.16.5.2 Slow Clock Using an External Clock
          1. 8.16.5.2.1 External RTC Digital Clock Requirements
        3. 8.16.5.3 Fast Clock (Fref) Using an External Crystal
          1. 8.16.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 8.16.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 8.16.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 8.16.6 Peripherals Timing
        1. 8.16.6.1  SPI
          1. 8.16.6.1.1 SPI Master
            1. 8.16.6.1.1.1 SPI Master Timing Parameters
          2. 8.16.6.1.2 SPI Slave
            1. 8.16.6.1.2.1 SPI Slave Timing Parameters
        2. 8.16.6.2  I2S
          1. 8.16.6.2.1 I2S Transmit Mode
            1. 8.16.6.2.1.1 I2S Transmit Mode Timing Parameters
          2. 8.16.6.2.2 I2S Receive Mode
            1. 8.16.6.2.2.1 I2S Receive Mode Timing Parameters
        3. 8.16.6.3  GPIOs
          1. 8.16.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1. 8.16.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V) (1) (1)
          2. 8.16.6.3.2 GPIO Input Transition Time Parameters
            1. 8.16.6.3.2.1 GPIO Input Transition Time Parameters
        4. 8.16.6.4  I2C
          1. 8.16.6.4.1 I2C Timing Parameters (1)
        5. 8.16.6.5  IEEE 1149.1 JTAG
          1. 8.16.6.5.1 JTAG Timing Parameters
        6. 8.16.6.6  ADC
          1. 8.16.6.6.1 ADC Electrical Specifications
        7. 8.16.6.7  Camera Parallel Port
          1. 8.16.6.7.1 Camera Parallel Port Timing Parameters
        8. 8.16.6.8  UART
        9. 8.16.6.9  SD Host
        10. 8.16.6.10 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  Power-Management Subsystem
    6. 9.6  Low-Power Operating Mode
    7. 9.7  Memory
      1. 9.7.1 External Memory Requirements
      2. 9.7.2 Internal Memory
        1. 9.7.2.1 SRAM
        2. 9.7.2.2 ROM
        3. 9.7.2.3 Flash Memory
        4. 9.7.2.4 Memory Map
    8. 9.8  Restoring Factory Default Configuration
    9. 9.9  Boot Modes
      1. 9.9.1 Boot Mode List
    10. 9.10 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Tools and Software
    3. 11.3 Firmware Updates
    4. 11.4 Device Nomenclature
    5. 11.5 Documentation Support
    6. 11.6 Support Resources
    7. 11.7 Trademarks
    8. 11.8 Electrostatic Discharge Caution
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.7.2.4 Memory Map

Table 9-5 describes the various MCU peripherals and how they are mapped to the processor memory. For more information on peripherals, see the API document.

Table 9-5 Memory Map
START ADDRESS END ADDRESS DESCRIPTION COMMENT
0x0000 0000 0x0007 FFFF On-chip ROM (bootloader + DriverLib)
0x0100 0000 0x010F FFFF On-chip flash (for user application code) CC3230SF device only
0x2000 0000 0x2003 FFFF Bit-banded on-chip SRAM
0x2200 0000 0x23FF FFFF Bit-band alias of 0x2000 0000 to 0x200F FFFF
0x4000 0000 0x4000 0FFF Watchdog timer A0
0x4000 4000 0x4000 4FFF GPIO port A0
0x4000 5000 0x4000 5FFF GPIO port A1
0x4000 6000 0x4000 6FFF GPIO port A2
0x4000 7000 0x4000 7FFF GPIO port A3
0x4000 C000 0x4000 CFFF UART A0
0x4000 D000 0x4000 DFFF UART A1
0x4002 0000 0x4000 07FF I2C A0 (master)
0x4002 0800 0x4002 0FFF I2C A0 (slave)
0x4002 4000 0x4002 4FFF GPIO group 4
0x4003 0000 0x4003 0FFF General-purpose timer A0
0x4003 1000 0x4003 1FFF General-purpose timer A1
0x4003 2000 0x4003 2FFF General-purpose timer A2
0x4003 3000 0x4003 3FFF General-purpose timer A3
0x400F 7000 0x400F 7FFF Configuration registers
0x400F E000 0x400F EFFF System control
0x400F F000 0x400F FFFF µDMA
0x4200 0000 0x43FF FFFF Bit band alias of 0x4000 0000 to 0x400F FFFF
0x4401 0000 0x4401 0FFF SDIO master
0x4401 8000 0x4401 8FFF Camera Interface
0x4401 C000 0x4401 DFFF McASP
0x4402 0000 0x4402 1FFF SSPI Used for external serial flash
0x4402 1000 0x4402 2FFF GSPI Used by application processor
0x4402 5000 0x4402 5FFF MCU reset clock manager
0x4402 6000 0x4402 6FFF MCU configuration space
0x4402 D000 0x4402 DFFF Global power, reset, and clock manager (GPRCM)
0x4402 E000 0x4402 EFFF MCU shared configuration
0x4402 F000 0x4402 FFFF Hibernate configuration
0x4403 0000 0x4403 FFFF Crypto range (includes apertures for all crypto-related blocks as follows)
0x4403 0000 0x4403 0FFF DTHE registers and TCP checksum
0x4403 5000 0x4403 5FFF MD5/SHA
0x4403 7000 0x4403 7FFF AES
0x4403 9000 0x4403 9FFF DES
0xE000 0000 0xE000 0FFF Instrumentation trace Macrocell™
0xE000 1000 0xE000 1FFF Data watchpoint and trace (DWT)
0xE000 2000 0xE000 2FFF Flash patch and breakpoint (FPB)
0xE000 E000 0xE000 EFFF NVIC
0xE004 0000 0xE004 0FFF Trace port interface unit (TPIU)
0xE004 1000 0xE004 1FFF Reserved for embedded trace macrocell (ETM)
0xE004 2000 0xE00F FFFF Reserved