SWRS243B February   2020  – May 2021 CC3235MODAS , CC3235MODASF , CC3235MODS , CC3235MODSF

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3235MODx and CC3235MODAx Pin Diagram
    2. 7.2 Pin Attributes and Pin Multiplexing
      1. 7.2.1 Module Pin Descriptions
    3. 7.3 Signal Descriptions
    4. 7.4 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    5. 7.5 Pad State After Application of Power to Chip, but Before Reset Release
    6. 7.6 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption (CC3235MODS and CC3235MODAS)
      1.      21
      2.      22
    5. 8.5  Current Consumption (CC3235MODSF and CC3235MODASF)
      1.      24
      2.      25
    6. 8.6  TX Power Control for 2.4 GHz Band
    7. 8.7  TX Power Control for 5 GHz
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics for GPIO Pins
      1. 8.9.1 Electrical Characteristics for Pin Internal Pullup and Pulldown (25°C)
    10. 8.10 CC3235MODAx Antenna Characteristics
    11. 8.11 WLAN Receiver Characteristics
      1.      33
      2.      34
    12. 8.12 WLAN Transmitter Characteristics
      1.      36
      2.      37
    13. 8.13 BLE and WLAN Coexistence Requirements
    14. 8.14 Reset Requirement
    15. 8.15 Thermal Resistance Characteristics for MOB and MON Packages
    16. 8.16 Timing and Switching Characteristics
      1. 8.16.1 Power-Up Sequencing
      2. 8.16.2 Power-Down Sequencing
      3. 8.16.3 Device Reset
      4. 8.16.4 Wake Up From Hibernate Timing
      5. 8.16.5 Peripherals Timing
        1. 8.16.5.1  SPI
          1. 8.16.5.1.1 SPI Master
          2. 8.16.5.1.2 SPI Slave
        2. 8.16.5.2  I2S
          1. 8.16.5.2.1 I2S Transmit Mode
          2. 8.16.5.2.2 I2S Receive Mode
        3. 8.16.5.3  GPIOs
          1. 8.16.5.3.1 GPIO Input Transition Time Parameters
        4. 8.16.5.4  I2C
        5. 8.16.5.5  IEEE 1149.1 JTAG
        6. 8.16.5.6  ADC
        7. 8.16.5.7  Camera Parallel Port
        8. 8.16.5.8  UART
        9. 8.16.5.9  External Flash Interface
        10. 8.16.5.10 SD Host
        11. 8.16.5.11 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Functional Block Diagram
    3. 9.3  Arm Cortex-M4 Processor Core Subsystem
    4. 9.4  Wi-Fi Network Processor Subsystem
      1. 9.4.1 WLAN
      2. 9.4.2 Network Stack
    5. 9.5  Security
    6. 9.6  FIPS 140-2 Level 1 Certification
    7. 9.7  Power-Management Subsystem
      1. 9.7.1 VBAT Wide-Voltage Connection
    8. 9.8  Low-Power Operating Mode
    9. 9.9  Memory
      1. 9.9.1 Internal Memory
        1. 9.9.1.1 SRAM
        2. 9.9.1.2 ROM
        3. 9.9.1.3 Flash Memory
        4. 9.9.1.4 Memory Map
    10. 9.10 Restoring Factory Default Configuration
    11. 9.11 Boot Modes
      1. 9.11.1 Boot Mode List
    12. 9.12 Hostless Mode
    13. 9.13 Device Certification and Qualification
      1. 9.13.1 FCC Certification and Statement
      2. 9.13.2 IC/ISED Certification and Statement
      3. 9.13.3 ETSI/CE Certification
      4. 9.13.4 MIC Certification
    14. 9.14 Module Markings
    15. 9.15 End Product Labeling
    16. 9.16 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Typical Application
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection (CC3235MODx only)
      3. 10.1.3 Typical Application Schematic (CC3235MODx)
      4. 10.1.4 Typical Application Schematic (CC3235MODAx)
    2. 10.2 Device Connection and Layout Fundamentals
      1. 10.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.2.2 Reset
      3. 10.2.3 Unused Pins
    3. 10.3 PCB Layout Guidelines
      1. 10.3.1 General Layout Recommendations
      2. 10.3.2 CC3235MODx RF Layout Recommendations
        1. 10.3.2.1 Antenna Placement and Routing
        2. 10.3.2.2 Transmission Line Considerations
      3. 10.3.3 CC3235MODAx RF Layout Recommendations
  11. 11Environmental Requirements and SMT Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 PCB Assembly Guide
      1. 11.4.1 PCB Land Pattern & Thermal Vias
      2. 11.4.2 SMT Assembly Recommendations
      3. 11.4.3 PCB Surface Finish Requirements
      4. 11.4.4 Solder Stencil
      5. 11.4.5 Package Placement
      6. 11.4.6 Solder Joint Inspection
      7. 11.4.7 Rework and Replacement
      8. 11.4.8 Solder Joint Voiding
    5. 11.5 Baking Conditions
    6. 11.6 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Development Tools and Software
    2. 12.2 Firmware Updates
    3. 12.3 Device Nomenclature
    4. 12.4 Documentation Support
    5. 12.5 Related Links
    6. 12.6 Support Resources
    7. 12.7 Trademarks
    8. 12.8 Electrostatic Discharge Caution
    9. 12.9 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
      3. 13.2.3 CC3235MODx Tape Specifications
      4. 13.2.4 CC3235MODAx Tape Specifications

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MOB|63
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.8 Low-Power Operating Mode

From a power-management perspective, the CC3235MODx and CC3235MODAx MCU comprises the following two independent subsystems:

  • Arm Cortex-M4 application processor subsystem
  • Networking subsystem

Each subsystem operates in one of several power states.

The Arm Cortex-M4 application processor runs the user application loaded from an internal serial flash, or on-module XIP flash (in CC3235MODSF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer functions.

The user program controls the power state of the application processor subsystem and can be in one of the five modes described in Table 9-2.

Table 9-2 User Program Modes
APPLICATION PROCESSOR (MCU) MODE(1) DESCRIPTION
MCU active mode MCU executing code at 80-MHz state rate.
MCU sleep mode The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity from any GPIO line or peripheral.
MCU LPDS mode State information is lost and only certain MCU-specific register configurations are retained. The MCU can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.) Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the wake-up source.
MCU hibernate mode The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly powered by the input supply is retained. The RTC keeps running and the MCU supports wakeup from an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15 ms plus the time to load the application from serial flash, which varies according to code size. In this mode, the MCU can be configured to wake up using the RTC timer or external event on a GPIO.
MCU shutdown mode The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the nRESET line is changed (low to shut down, high to turn on).
(1) Modes are listed in order of power consumption, with highest power modes listed first.

 

The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network activity, the NWP sleeps most of the time and wakes up only for beacon reception (see
Table 9-3).

Table 9-3 Networking Subsystem Modes
NETWORK PROCESSOR MODEDESCRIPTION
Network active mode
(processing layer 3, 2, and 1)		Transmitting or receiving IP protocol packets
Network active mode
(processing layer 2 and 1)		Transmitting or receiving MAC management frames; IP processing not required.
Network active listen modeSpecial power optimized active mode for receiving beacon frames (no other frames supported)
Network connected IdleA composite mode that implements 802.11 infrastructure power save operation. The CC3235MODx and CC3235MODAx NWPs automatically go into LPDS mode between beacons and then wakes to active listen mode to receive a beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS mode and the cycle repeats.
Network LPDS modeLow-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake up.
Network disabledThe network is disabled

 

The operation of the application and network processor ensures that the module remains in the lowest power mode most of the time to preserve battery life.

The following examples show the use of the power modes in applications:

  • A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but sends and receives little data spends most of the time in connected idle, which is a composite of receiving a beacon frame and waiting for the next beacon.
  • A product that is not continuously connected to the network but instead wakes up periodically (for example, every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to transmit data.