SLAS554I May   2009  – September 2018 CC430F5133 , CC430F5135 , CC430F5137 , CC430F6125 , CC430F6126 , CC430F6127 , CC430F6135 , CC430F6137

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 CC430F613x and CC430F612x Terminal Functions
      2. Table 4-2 CC430F513x Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics – Low-Power Mode Supply Currents
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Thermal Resistance Characteristics, CC430F51xx
    10. 5.10 Thermal Resistance Characteristics, CC430F61xx
    11. 5.11 Digital Inputs
    12. 5.12 Digital Outputs
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 USCI (UART Mode) Clock Frequency
    28. 5.28 USCI (UART Mode)
    29. 5.29 USCI (SPI Master Mode) Clock Frequency
    30. 5.30 USCI (SPI Master Mode)
    31. 5.31 USCI (SPI Slave Mode)
    32. 5.32 USCI (I2C Mode)
    33. 5.33 LCD_B Operating Conditions
    34. 5.34 LCD_B Electrical Characteristics
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Flash Memory
    44. 5.44 JTAG and Spy-Bi-Wire Interface
    45. 5.45 RF1A CC1101-Based Radio Parameters
      1. 5.45.1  Recommended Operating Conditions
      2. 5.45.2  RF Crystal Oscillator, XT2
      3. 5.45.3  Current Consumption, Reduced-Power Modes
      4. 5.45.4  Current Consumption, Receive Mode
      5. 5.45.5  Current Consumption, Transmit Mode
      6. 5.45.6  Typical TX Current Consumption, 315 MHz
      7. 5.45.7  Typical TX Current Consumption, 433 MHz
      8. 5.45.8  Typical TX Current Consumption, 868 MHz
      9. 5.45.9  Typical TX Current Consumption, 915 MHz
      10. 5.45.10 RF Receive, Overall
      11. 5.45.11 RF Receive, 315 MHz
      12. 5.45.12 RF Receive, 433 MHz
      13. 5.45.13 RF Receive, 868 or 915 MHz
      14. 5.45.14 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
      15. 5.45.15 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
      16. 5.45.16 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
      17. 5.45.17 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
      18. 5.45.18 RF Transmit
      19. 5.45.19 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      20. 5.45.20 Typical Output Power, 315 MHz
      21. 5.45.21 Typical Output Power, 433 MHz
      22. 5.45.22 Typical Output Power, 868 MHz
      23. 5.45.23 Typical Output Power, 915 MHz
      24. 5.45.24 Frequency Synthesizer Characteristics
      25. 5.45.25 Typical RSSI_offset Values
  6. 6Detailed Description
    1. 6.1  Sub-1 GHz Radio
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Peripherals
      1. 6.10.1  Oscillator and System Clock
      2. 6.10.2  Power-Management Module (PMM)
      3. 6.10.3  Digital I/O
      4. 6.10.4  Port Mapping Controller
      5. 6.10.5  System Module (SYS)
      6. 6.10.6  DMA Controller
      7. 6.10.7  Watchdog Timer (WDT_A)
      8. 6.10.8  CRC16
      9. 6.10.9  Hardware Multiplier
      10. 6.10.10 AES128 Accelerator
      11. 6.10.11 Universal Serial Communication Interface (USCI)
      12. 6.10.12 TA0
      13. 6.10.13 TA1
      14. 6.10.14 Real-Time Clock (RTC_A)
      15. 6.10.15 Voltage Reference (REF)
      16. 6.10.16 LCD_B (Only CC430F613x and CC430F612x)
      17. 6.10.17 Comparator_B
      18. 6.10.18 ADC12_A (Only CC430F613x and CC430F513x)
      19. 6.10.19 Embedded Emulation Module (EEM) (S Version)
      20. 6.10.20 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      6. 6.11.6  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      8. 6.11.8  Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      9. 6.11.9  Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptor
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuits
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals for the CC430F613x and CC430F612x devices. See Table 4-2 for the CC430F513x devices.

Table 4-1 CC430F613x and CC430F612x Terminal Functions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
P1.7/ PM_UCA0CLK/ PM_UCB0STE/ R03 1 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable
Input/output port of lowest analog LCD voltage (V5)
P1.6/ PM_UCA0TXD/ PM_UCA0SIMO/ R13/LCDREF 2 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
P1.5/ PM_UCA0RXD/ PM_UCA0SOMI/ R23 3 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/ R33 4 I/O LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION: Must be connected to VSS if not used.
COM0 5 O LCD common output COM0 for LCD backplane
P5.7/ COM1/ S26 6 I/O General-purpose digital I/O
LCD common output COM1 for LCD backplane
LCD segment output S26
P5.6/ COM2/ S25 7 I/O General-purpose digital I/O
LCD common output COM2 for LCD backplane
LCD segment output S25
P5.5/ COM3/ S24 8 I/O General-purpose digital I/O
LCD common output COM3 for LCD backplane
LCD segment output S24
P5.4/ S23 9 I/O General-purpose digital I/O
LCD segment output S23
VCORE 10 Regulated core power supply
DVCC 11 Digital power supply
P1.4/ PM_UCB0CLK/ PM_UCA0STE/ S22 12 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output
Default mapping: USCI_A0 SPI slave transmit enable
LCD segment output S22
P1.3/ PM_UCB0SIMO/ PM_UCB0SDA/ S21 13 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out
Default mapping: USCI_B0 I2C data
LCD segment output S21
P1.2/ PM_UCB0SOMI/ PM_UCB0SCL/ S20 14 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in
Default mapping: UCSI_B0 I2C clock
LCD segment output S20
P1.1/ PM_RFGDO2/ S19 15 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output
LCD segment output S19
P1.0/ PM_RFGDO0/ S18 16 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output
LCD segment output S18
P3.7/ PM_SMCLK/ S17 17 I/O General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output
LCD segment output S17
P3.6/ PM_RFGDO1/ S16 18 I/O General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output
LCD segment output S16
P3.5/ PM_TA0CCR4A/ S15 19 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input
LCD segment output S15
P3.4/ PM_TA0CCR3A/ S14 20 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input
LCD segment output S14
P3.3/ PM_TA0CCR2A/ S13 21 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input
LCD segment output S13
P3.2/ PM_TA0CCR1A/ S12 22 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input
LCD segment output S12
P3.1/ PM_TA0CCR0A/ S11 23 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input
LCD segment output S11
P3.0/ PM_CBOUT0/ PM_TA0CLK/ S10 24 I/O General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA0 clock input
LCD segment output S10
DVCC 25 Digital power supply
P4.7/ S9 26 I/O General-purpose digital I/O
LCD segment output S9
P4.6/ S8 27 I/O General-purpose digital I/O
LCD segment output S8
P4.5/ S7 28 I/O General-purpose digital I/O
LCD segment output S7
P4.4/ S6 29 I/O General-purpose digital I/O
LCD segment output S6
P4.3/ S5 30 I/O General-purpose digital I/O
LCD segment output S5
P4.2/ S4 31 I/O General-purpose digital I/O
LCD segment output S4
P4.1/ S3 32 I/O General-purpose digital I/O
LCD segment output S3
P4.0/ S2 33 I/O General-purpose digital I/O
LCD segment output S2
P5.3/ S1 34 I/O General-purpose digital I/O
LCD segment output S1
P5.2/ S0 35 I/O General-purpose digital I/O
LCD segment output S0
RF_XIN 36 I Input terminal for RF crystal oscillator, or external clock input
RF_XOUT 37 O Output terminal for RF crystal oscillator
AVCC_RF 38 Radio analog power supply
AVCC_RF 39 Radio analog power supply
RF_P 40 RF I/O Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode
RF_N 41 RF I/O Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode
AVCC_RF 42 Radio analog power supply
AVCC_RF 43 Radio analog power supply
RBIAS 44 External bias resistor for radio reference current
GUARD 45 Power supply connection for digital noise isolation
PJ.0/ TDO 46 I/O General-purpose digital I/O
Test data output port
PJ.1/ TDI/ TCLK 47 I/O General-purpose digital I/O
Test data input or test clock input
PJ.2/ TMS 48 I/O General-purpose digital I/O
Test mode select
PJ.3/ TCK 49 I/O General-purpose digital I/O
Test clock
TEST/ SBWTCK 50 I Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
RST/NMI/ SBWTDIO 51 I/O Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
DVCC 52 Digital power supply
AVSS 53 Analog ground supply for ADC12
P5.1/ XOUT 54 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN 55 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
AVCC 56 Analog power supply
P2.7/ PM_ADC12CLK/ PM_DMAE0/ CB7 (/A7) 57 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC12CLK output
Default mapping: DMA external trigger input
Comparator_B input CB7
Analog input A7 – 12-bit ADC (CC430F613x only)
P2.6/ PM_ACLK/ CB6 (/A6) 58 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output
Comparator_B input CB6
Analog input A6 – 12-bit ADC (CC430F613x only)
P2.5/ PM_SVMOUT/ CB5
(/A5/ VREF+/ VeREF+)		 59 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
Comparator_B input CB5
Analog input A5 – 12-bit ADC (CC430F613x only)
Output of reference voltage to the ADC (CC430F613x only)
Input for an external reference voltage to the ADC (CC430F613x only)
P2.4/ PM_RTCCLK/ CB4
(/A4/ VREF-/ VeREF-)		 60 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
Comparator_B input CB4
Analog input A4 – 12-bit ADC (CC430F613x only)
Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage (CC430F613x only)
P2.3/ PM_TA1CCR2A/ CB3 (/A3) 61 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
Comparator_B input CB3
Analog input A3 – 12-bit ADC (CC430F613x only)
P2.2/ PM_TA1CCR1A/ CB2 (/A2) 62 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
Comparator_B input CB2
Analog input A2 – 12-bit ADC (CC430F613x only)
P2.1/ PM_TA1CCR0A/ CB1 (/A1) 63 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
Comparator_B input CB1
Analog input A1 – 12-bit ADC (CC430F613x only)
P2.0/ PM_CBOUT1/ PM_TA1CLK/ CB0 (/A0) 64 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA1 clock input
Comparator_B input CB0
Analog input A0 – 12-bit ADC (CC430F613x only)
VSS, Exposed die attach pad Ground supply
CAUTION: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.
(1) I = input, O = output

Table 4-2 describes the signals for the CC430F513x devices. See Table 4-1 for the CC430F613x and CC430F612x devices.

Table 4-2 CC430F513x Terminal Functions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
P2.2/ PM_TA1CCR1A/ CB2/ A2 1 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
Comparator_B input CB2
Analog input A2 – 12-bit ADC
P2.1/ PM_TA1CCR0A/ CB1/ A1 2 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
Comparator_B input CB1
Analog input A1 – 12-bit ADC
P2.0/ PM_CBOUT1/ PM_TA1CLK/ CB0/ A0 3 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA1 clock input
Comparator_B input CB0
Analog input A0 – 12-bit ADC
P1.7/ PM_UCA0CLK/ PM_UCB0STE 4 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output
Default mapping: USCI_B0 SPI slave transmit enable
P1.6/ PM_UCA0TXD/ PM_UCA0SIMO 5 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
P1.5/ PM_UCA0RXD/ PM_UCA0SOMI 6 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data
Default mapping: USCI_A0 SPI slave out master in
VCORE 7 Regulated core power supply
DVCC 8 Digital power supply
P1.4/ PM_UCB0CLK/ PM_UCA0STE 9 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output
Default mapping: USCI_A0 SPI slave transmit enable
P1.3/ PM_UCB0SIMO/ PM_UCB0SDA 10 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out
Default mapping: USCI_B0 I2C data
P1.2/ PM_UCB0SOMI/ PM_UCB0SCL 11 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in
Default mapping: UCSI_B0 I2C clock
P1.1/ PM_RFGDO2 12 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output
P1.0/ PM_RFGDO0 13 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output
P3.7/ PM_SMCLK 14 I/O General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output
P3.6/ PM_RFGDO1 15 I/O General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output
P3.5/ PM_TA0CCR4A 16 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input
P3.4/ PM_TA0CCR3A 17 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input
P3.3/ PM_TA0CCR2A 18 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input
P3.2/ PM_TA0CCR1A 19 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input
P3.1/ PM_TA0CCR0A 20 I/O General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input
P3.0/ PM_CBOUT0/ PM_TA0CLK 21 I/O General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output
Default mapping: TA0 clock input
DVCC 22 Digital power supply
P2.7/ PM_ADC12CLK/ PM_DMAE0 23 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC12CLK output
Default mapping: DMA external trigger input
P2.6/ PM_ACLK 24 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output
RF_XIN 25 I Input terminal for RF crystal oscillator, or external clock input
RF_XOUT 26 O Output terminal for RF crystal oscillator
AVCC_RF 27 Radio analog power supply
AVCC_RF 28 Radio analog power supply
RF_P 29 RF I/O Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode
RF_N 30 RF I/O Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode
AVCC_RF 31 Radio analog power supply
AVCC_RF 32 Radio analog power supply
RBIAS 33 External bias resistor for radio reference current
GUARD 34 Power supply connection for digital noise isolation
PJ.0/ TDO 35 I/O General-purpose digital I/O
Test data output port
PJ.1/ TDI/ TCLK 36 I/O General-purpose digital I/O
Test data input or test clock input
PJ.2/ TMS 37 I/O General-purpose digital I/O
Test mode select
PJ.3/ TCK 38 I/O General-purpose digital I/O
Test clock
TEST/ SBWTCK 39 I Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
RST/NMI/ SBWTDIO 40 I/O Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
DVCC 41 Digital power supply
AVSS 42 Analog ground supply for ADC12
P5.1/ XOUT 43 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
P5.0/ XIN 44 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
AVCC 45 Analog power supply
P2.5/ PM_SVMOUT/ CB5/
A5/ VREF+/ VeREF+		 46 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
Comparator_B input CB5
Analog input A5 – 12-bit ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
P2.4/ PM_RTCCLK/ CB4/
A4/ VREF-/ VeREF-		 47 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
Comparator_B input CB4
Analog input A4 – 12-bit ADC
Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage
P2.3/ PM_TA1CCR2A/ CB3/ A3 48 I/O General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
Comparator_B input CB3
Analog input A3 – 12-bit ADC
VSS, Exposed die attach pad Ground supply
The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.
(1) I = input, O = output