SLAS554I May   2009  – September 2018 CC430F5133 , CC430F5135 , CC430F5137 , CC430F6125 , CC430F6126 , CC430F6127 , CC430F6135 , CC430F6137

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 CC430F613x and CC430F612x Terminal Functions
      2. Table 4-2 CC430F513x Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics – Low-Power Mode Supply Currents
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Thermal Resistance Characteristics, CC430F51xx
    10. 5.10 Thermal Resistance Characteristics, CC430F61xx
    11. 5.11 Digital Inputs
    12. 5.12 Digital Outputs
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 USCI (UART Mode) Clock Frequency
    28. 5.28 USCI (UART Mode)
    29. 5.29 USCI (SPI Master Mode) Clock Frequency
    30. 5.30 USCI (SPI Master Mode)
    31. 5.31 USCI (SPI Slave Mode)
    32. 5.32 USCI (I2C Mode)
    33. 5.33 LCD_B Operating Conditions
    34. 5.34 LCD_B Electrical Characteristics
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Flash Memory
    44. 5.44 JTAG and Spy-Bi-Wire Interface
    45. 5.45 RF1A CC1101-Based Radio Parameters
      1. 5.45.1  Recommended Operating Conditions
      2. 5.45.2  RF Crystal Oscillator, XT2
      3. 5.45.3  Current Consumption, Reduced-Power Modes
      4. 5.45.4  Current Consumption, Receive Mode
      5. 5.45.5  Current Consumption, Transmit Mode
      6. 5.45.6  Typical TX Current Consumption, 315 MHz
      7. 5.45.7  Typical TX Current Consumption, 433 MHz
      8. 5.45.8  Typical TX Current Consumption, 868 MHz
      9. 5.45.9  Typical TX Current Consumption, 915 MHz
      10. 5.45.10 RF Receive, Overall
      11. 5.45.11 RF Receive, 315 MHz
      12. 5.45.12 RF Receive, 433 MHz
      13. 5.45.13 RF Receive, 868 or 915 MHz
      14. 5.45.14 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
      15. 5.45.15 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
      16. 5.45.16 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
      17. 5.45.17 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
      18. 5.45.18 RF Transmit
      19. 5.45.19 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      20. 5.45.20 Typical Output Power, 315 MHz
      21. 5.45.21 Typical Output Power, 433 MHz
      22. 5.45.22 Typical Output Power, 868 MHz
      23. 5.45.23 Typical Output Power, 915 MHz
      24. 5.45.24 Frequency Synthesizer Characteristics
      25. 5.45.25 Typical RSSI_offset Values
  6. 6Detailed Description
    1. 6.1  Sub-1 GHz Radio
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Peripherals
      1. 6.10.1  Oscillator and System Clock
      2. 6.10.2  Power-Management Module (PMM)
      3. 6.10.3  Digital I/O
      4. 6.10.4  Port Mapping Controller
      5. 6.10.5  System Module (SYS)
      6. 6.10.6  DMA Controller
      7. 6.10.7  Watchdog Timer (WDT_A)
      8. 6.10.8  CRC16
      9. 6.10.9  Hardware Multiplier
      10. 6.10.10 AES128 Accelerator
      11. 6.10.11 Universal Serial Communication Interface (USCI)
      12. 6.10.12 TA0
      13. 6.10.13 TA1
      14. 6.10.14 Real-Time Clock (RTC_A)
      15. 6.10.15 Voltage Reference (REF)
      16. 6.10.16 LCD_B (Only CC430F613x and CC430F612x)
      17. 6.10.17 Comparator_B
      18. 6.10.18 ADC12_A (Only CC430F613x and CC430F513x)
      19. 6.10.19 Embedded Emulation Module (EEM) (S Version)
      20. 6.10.20 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      6. 6.11.6  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      8. 6.11.8  Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      9. 6.11.9  Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptor
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuits
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.36 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fADC12CLK ADC conversion clock For specified performance of ADC12 linearity parameters using an external reference voltage or AVCC as reference(1) 2.2 V, 3 V 0.45 4.8 5.0 MHz
For specified performance of ADC12 linearity parameters using the internal reference(2) 0.45 2.4 4.0
For specified performance of ADC12 linearity parameters using the internal reference(3) 0.45 2.4 2.7
fADC12OSC Internal ADC12 oscillator(5) ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz
tCONVERT Conversion time REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz		 2.2 V, 3 V 2.4 3.1 µs
External fADC12CLK from ACLK, MCLK or SMCLK, ADC12SSEL ≠ 0 13 × 1 / fADC12CLK
tSample Sampling time RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = (RS + RI) × CI(4) 		2.2 V, 3 V 1000 ns
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC divided by 2.
(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
(5) The ADC12OSC is sourced directly from MODOSC inside the UCS.