SLAS555B June 2012 – September 2018 CC430F5123 , CC430F5125 , CC430F5143 , CC430F5145 , CC430F5147 , CC430F6147
PRODUCTION DATA.
Table 4-1 describes the signals for the CC430F614x devices.
TERMINAL | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
P1.7/ PM_UCA0CLK/ PM_UCB0STE/ R03 | 1 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable Input/output port of lowest analog LCD voltage (V5) |
P1.6/ PM_UCA0TXD/ PM_UCA0SIMO/ R13/ LCDREF | 2 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out Input/output port of third most positive analog LCD voltage (V3 or V4) External reference voltage input for regulated LCD voltage |
P1.5/ PM_UCA0RXD/ PM_UCA0SOMI/ R23 | 3 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in Input/output port of second most positive analog LCD voltage (V2) |
LCDCAP/ R33 | 4 | I/O | LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1) CAUTION: Must be connected to VSS if not used. |
COM0 | 5 | O | LCD common output COM0 for LCD backplane |
P5.7/ COM1/ S26 | 6 | I/O | General-purpose digital I/O
LCD common output COM1 for LCD backplane LCD segment output S26 |
P5.6/ COM2/ S25 | 7 | I/O | General-purpose digital I/O
LCD common output COM2 for LCD backplane LCD segment output S25 |
P5.5/ COM3/ S24 | 8 | I/O | General-purpose digital I/O
LCD common output COM3 for LCD backplane LCD segment output S24 |
P5.4/ S23 | 9 | I/O | General-purpose digital I/O
LCD segment output S23 |
VCORE | 10 | Regulated core power supply | |
DVCC | 11 | Digital power supply | |
P1.4/ PM_UCB0CLK/ PM_UCA0STE/ S22 | 12 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable LCD segment output S22 |
P1.3/ PM_UCB0SIMO/ PM_UCB0SDA/ S21 | 13 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out; USCI_B0 I2C data LCD segment output S21 |
P1.2/ PM_UCB0SOMI/ PM_UCB0SCL/ S20 | 14 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in; UCSI_B0 I2C clock LCD segment output S20 |
P1.1/ PM_RFGDO2/ S19 | 15 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output LCD segment output S19 |
P1.0/ PM_RFGDO0/ S18 | 16 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output LCD segment output S18 |
P3.7/ PM_SMCLK/ S17 | 17 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output LCD segment output S17 |
P3.6/ PM_RFGDO1/ S16 | 18 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output LCD segment output S16 |
P3.5/ PM_TA0CCR4A/ S15 | 19 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input LCD segment output S15 |
P3.4/ PM_TA0CCR3A/ S14 | 20 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input LCD segment output S14 |
P3.3/ PM_TA0CCR2A/ S13 | 21 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input LCD segment output S13 |
P3.2/ PM_TA0CCR1A/ S12 | 22 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input LCD segment output S12 |
P3.1/ PM_TA0CCR0A/ S11 | 23 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input LCD segment output S11 |
P3.0/ PM_CBOUT0/ PM_TA0CLK/ S10 | 24 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output; TA0 clock input LCD segment output S10 |
DVCC | 25 | Digital power supply | |
P4.7/ S9 | 26 | I/O | General-purpose digital I/O
LCD segment output S9 |
P4.6/ S8 | 27 | I/O | General-purpose digital I/O
LCD segment output S8 |
P4.5/ S7 | 28 | I/O | General-purpose digital I/O
LCD segment output S7 |
P4.4/ S6 | 29 | I/O | General-purpose digital I/O
LCD segment output S6 |
P4.3/ S5 | 30 | I/O | General-purpose digital I/O
LCD segment output S5 |
P4.2/ S4 | 31 | I/O | General-purpose digital I/O
LCD segment output S4 |
P4.1/ S3 | 32 | I/O | General-purpose digital I/O
LCD segment output S3 |
P4.0/ S2 | 33 | I/O | General-purpose digital I/O
LCD segment output S2 |
P5.3/ S1 | 34 | I/O | General-purpose digital I/O
LCD segment output S1 |
P5.2/ S0 | 35 | I/O | General-purpose digital I/O
LCD segment output S0 |
RF_XIN | 36 | I | Input terminal for RF crystal oscillator or external clock input |
RF_XOUT | 37 | O | Output terminal for RF crystal oscillator |
AVCC_RF | 38 | Radio analog power supply | |
AVCC_RF | 39 | Radio analog power supply | |
RF_P | 40 | RF I/O | Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode |
RF_N | 41 | RF I/O | Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode |
AVCC_RF | 42 | Radio analog power supply | |
AVCC_RF | 43 | Radio analog power supply | |
RBIAS | 44 | External bias resistor for radio reference current | |
GUARD | 45 | Power supply connection for digital noise isolation | |
PJ.0/ TDO | 46 | I/O | General-purpose digital I/O
Test data output port |
PJ.1/ TDI/ TCLK | 47 | I/O | General-purpose digital I/O
Test data input or test clock input |
PJ.2/ TMS | 48 | I/O | General-purpose digital I/O
Test mode select |
PJ.3/ TCK | 49 | I/O | General-purpose digital I/O
Test clock |
TEST/ SBWTCK | 50 | I | Test mode pin - select digital I/O on JTAG pins
Spy-Bi-Wire input clock |
RST/NMI/ SBWTDIO | 51 | I/O | Reset input active low
Nonmaskable interrupt input Spy-Bi-Wire data input/output |
DVCC | 52 | Digital power supply | |
AVSS | 53 | Analog ground supply for ADC10 | |
P5.1/ XOUT | 54 | I/O | General-purpose digital I/O
Output terminal of crystal oscillator XT1 |
P5.0/ XIN | 55 | I/O | General-purpose digital I/O
Input terminal for crystal oscillator XT1 |
AVCC | 56 | Analog power supply | |
P2.7/ PM_ADC10CLK/ PM_DMAE0/ CB7 (/A7) | 57 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC10CLK output; DMA external trigger input Comparator_B input CB7 Analog input A7 for 10-bit ADC |
P2.6/ PM_ACLK/ CB6 (/A6) | 58 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output Comparator_B input CB6 Analog input A6 for 10-bit ADC |
P2.5/ PM_SVMOUT/ CB5
(/A5/ VREF+/ VeREF+) |
59 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output Comparator_B input CB5 Analog input A5 for 10-bit ADC Output of reference voltage to the ADC Positive terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage |
P2.4/ PM_RTCCLK/ CB4
(/A4/ VeREF-) |
60 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output Comparator_B input CB4 Analog input A4 for 10-bit ADC Negative terminal for the ADC reference voltage for an external applied reference voltage |
P2.3/ PM_TA1CCR2A/ CB3 (/A3) | 61 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input Comparator_B input CB3 Analog input A3 for 10-bit ADC |
P2.2/ PM_TA1CCR1A/ CB2 (/A2) | 62 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input Comparator_B input CB2 Analog input A2 for 10-bit ADC |
P2.1/PM_TA1CCR0A/CB1(/A1) | 63 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input Comparator_B input CB1 Analog input A1 for 10-bit ADC |
P2.0/ PM_CBOUT1/ PM_TA1CLK/ CB0 (/A0) | 64 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output; TA1 clock input Comparator_B input CB0 Analog input A0 for 10-bit ADC |
VSS - Exposed die attach pad | Ground supply
CAUTION: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip. |
Table 4-2 describes the signals for the CC430F514x and CC430F512x devices.
TERMINAL | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
P2.2/ PM_TA1CCR1A/ CB2/ (A2) | 1 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input Comparator_B input CB2 Analog input A2 for 10-bit ADC (only CC430F514x) |
P2.1/ PM_TA1CCR0A/ CB1/ (A1) | 2 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input Comparator_B input CB1 Analog input A1 for 10-bit ADC (only CC430F514x) |
P2.0/ PM_CBOUT1/ PM_TA1CLK/ CB0/ (A0) | 3 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Comparator_B output; TA1 clock input Comparator_B input CB0 Analog input A0 for 10-bit ADC (only CC430F514x) |
P1.7/ PM_UCA0CLK/ PM_UCA0STE | 4 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable |
P1.6/ PM_UCA0TXD/ PM_UCA0SIMO | 5 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out |
P1.5/ PM_UCA0RXD/ PM_UCA0SOMI | 6 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in |
VCORE | 7 | Regulated core power supply | |
DVCC | 8 | Digital power supply | |
P1.4/ PM_UCB0CLK/ PM_UCA0STE | 9 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable |
P1.3/ PM_UCB0SIMO/ PM_UCB0SDA | 10 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in master out; USCI_B0 I2C data |
P1.2/ PM_UCB0SOMI/ PM_UCB0SCL | 11 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out master in; UCSI_B0 I2C clock |
P1.1/ PM_RFGDO2 | 12 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO2 output |
P1.0/ PM_RFGDO0 | 13 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Radio GDO0 output |
P3.7/ PM_SMCLK | 14 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: SMCLK output |
P3.6/ PM_RFGDO1 | 15 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: Radio GDO1 output |
P3.5/ PM_TA0CCR4A | 16 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR4 compare output or capture input |
P3.4/ PM_TA0CCR3A | 17 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR3 compare output or capture input |
P3.3/ PM_TA0CCR2A | 18 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR2 compare output or capture input |
P3.2/ PM_TA0CCR1A | 19 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR1 compare output or capture input |
P3.1/ PM_TA0CCR0A | 20 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: TA0 CCR0 compare output or capture input |
P3.0/ PM_CBOUT0/ PM_TA0CLK | 21 | I/O | General-purpose digital I/O with mappable secondary function
Default mapping: Comparator_B output; TA0 clock input |
DVCC | 22 | Digital power supply | |
P2.7/ PM_ADC10CLK/ PM_DMAE0 | 23 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ADC10CLK output; DMA external trigger input |
P2.6/ PM_ACLK | 24 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output |
RF_XIN | 25 | I | Input terminal for RF crystal oscillator, or external clock input |
RF_XOUT | 26 | O | Output terminal for RF crystal oscillator |
AVCC_RF | 27 | Radio analog power supply | |
AVCC_RF | 28 | Radio analog power supply | |
RF_P | 29 | RF I/O | Positive RF input to LNA in receive mode
Positive RF output from PA in transmit mode |
RF_N | 30 | RF I/O | Negative RF input to LNA in receive mode
Negative RF output from PA in transmit mode |
AVCC_RF | 31 | Radio analog power supply | |
AVCC_RF | 32 | Radio analog power supply | |
RBIAS | 33 | External bias resistor for radio reference current | |
GUARD | 34 | Power supply connection for digital noise isolation | |
PJ.0/ TDO | 35 | I/O | General-purpose digital I/O
Test data output port |
PJ.1/ TDI/ TCLK | 36 | I/O | General-purpose digital I/O
Test data input or test clock input |
PJ.2/ TMS | 37 | I/O | General-purpose digital I/O
Test mode select |
PJ.3/ TCK | 38 | I/O | General-purpose digital I/O
Test clock |
TEST/ SBWTCK | 39 | I | Test mode pin - select digital I/O on JTAG pins
Spy-Bi-Wire input clock |
RST/NMI/ SBWTDIO | 40 | I/O | Reset input active low
Nonmaskable interrupt input Spy-Bi-Wire data input/output |
DVCC | 41 | Digital power supply | |
AVSS | 42 | Analog ground supply for ADC10 | |
P5.1/ XOUT | 43 | I/O | General-purpose digital I/O
Output terminal of crystal oscillator XT1 |
P5.0/ XIN | 44 | I/O | General-purpose digital I/O
Input terminal for crystal oscillator XT1 |
AVCC | 45 | Analog power supply | |
P2.5/ PM_SVMOUT/ CB5/
(A5/ VREF+/VeREF+) |
46 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output Comparator_B input CB5 Analog input A5 for 10-bit ADC (only CC430F514x) Positive terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage (only CC430F514x) |
P2.4/ PM_RTCCLK/ CB4/
(A4/ VeREF-) |
47 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output Comparator_B input CB4 Analog input A4 for 10-bit ADC (only CC430F514x) Negative terminal for the ADC reference voltage for an external applied reference voltage (only CC430F514x) |
P2.3/ PM_TA1CCR2A/ CB3/ (A3) | 48 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input Comparator_B input CB3 Analog input A3 for 10-bit ADC (only CC430F514x) |
VSS - Exposed die attach pad | Ground supply
CAUTION: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip. |