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  • CD40106B CMOS Hex Schmitt-Trigger Inverters

    • SCHS097F November   1998  – March 2017 CD40106B

      PRODUCTION DATA.  

  • CONTENTS
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  • CD40106B CMOS Hex Schmitt-Trigger Inverters
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Static
    6. 6.6 Electrical Characteristics: Dynamic
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Wave Shaper
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Monostable Multivibrator
      3. 9.2.3 Astable Multivibrator
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • N|14
    • MPDI002C
  • PW|14
    • MPDS360A
  • NS|14
    • MSOP002A
  • D|14
    • MPDS177H
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • schs097f_oa
  • schs097f_pm
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  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
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DATA SHEET

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features

  • Schmitt-Trigger Inputs
  • Hysteresis Voltage (Typical):
    • 0.9 V at VDD = 5 V
    • 2.3 V at VDD = 10 V
    • 3.5 V at VDD = 15 V
  • Noise Immunity Greater Than 50%
  • No Limit On Input Rise and Fall Times
  • Standardized, Symmetrical Output Characteristics
  • For Quiescent Current at 20 V
  • Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range:
    • 100 nA at 18 V and 25°C
  • Low VDD and VSS Current During Slow Input Ramp
  • 5-V, 10-V, and 15-V Parametric Ratings

2 Applications

  • Wave and Pulse Shapers
  • High-Noise-Environment Systems
  • Monostable Multivibrators
  • Astable Multivibrators

3 Description

The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH).

The CD40106B device is supplied in ceramic packaging (J) as well as standard packaging (D, N, NS, PW). All CD40106B devices are rated for –55°C to +125°C ambient temperature operation.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CD40106BF CDIP (14) 6.92 mm x 19.94 mm
CD40106BE PDIP (14) 6.30 mm x 19.31 mm
CD40106BM SOIC (14) 3.90 mm x 8.65 mm
CD40106BNSR SO (14) 5.30 mm x 10.20 mm
CD40106BPWR TSSOP (14) 4.40 mm x 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram

CD40106B Logic_Diag_SCHS097.gif
All inputs protected by the protection network shown to the right

4 Revision History

Changes from E Revision (September 2016) to F Revision

  • Changed incorrect pin descriptions to match package drawing Go

Changes from D Revision (August 2003) to E Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Added Thermal Information tableGo

5 Pin Configuration and Functions

D, J, N, NS, PW Packages
14-Pin SOIC, CDIP, PDIP, SO, TSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 A I Channel A input
2 G = A O Channel A inverted output
3 B I Channel B input
4 H = B O Channel B inverted output
5 C I Channel C input
6 I = C O Channel C inverted input
7 VSS — Ground
8 J = D O Channel D inverted output
9 D I Channel D input
10 K = E O Channel E inverted output
11 E I Channel E input
12 L = F O Channel F inverted output
13 F I Channel F input
14 VDD — Power supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DC supply voltage, VDD(2) –0.5 20 V
Input voltage, all inputs –0.5 VDD + 0.5 V
DC input current, any one input ±10 mA
Power dissipation, PD TA = –55°C to +100°C 500 mW
TA = 100°C to 125°C(3) 200
Device dissipation per output transistor 100 mW
Maximum junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages referenced to VSS terminal
(3) Derate linearity at 12 mW/°C

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage 3 18 V
Operating temperature, TA –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) CD40106B UNIT
D (SOIC) N (PDIP) NS (SO) PW (TSSOP)
14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient
thermal resistance 		86.1 51.3 83.5 114.1 °C/W
RθJC(top) Junction-to-case (top)
thermal resistance 		44.3 38.6 41.5 39.1 °C/W
RθJB Junction-to-board
thermal resistance 		40.6 31.2 42.2 56.9 °C/W
ψJT Junction-to-top
characterization parameter 		11.6 23.4 13.1 3.1 °C/W
ψJB Junction-to-board
characterization parameter 		40.3 31.3 41.8 56.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: Static

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDDmax Quiescent device current VIN = 0 or 5, VDD = 5 TA = –55°C 1 µA
TA = –40°C 1
TA = 25°C 0.02 1
TA = 85°C 30
TA = 125°C 30
VIN = 0 or 10, VDD = 10 TA = –55°C 2
TA = –40°C 2
TA = 25°C 0.02 2
TA = 85°C 60
TA = 125°C 60
VIN = 0 or 15, VDD = 15 TA = –55°C 4
TA = –40°C 4
TA = 25°C 0.02 4
TA = 85°C 120
TA = 125°C 120
VIN = 0 or 20, VDD = 20 TA = –55°C 20
TA = –40°C 20
TA = 25°C 0.04 20
TA = 85°C 600
TA = 125°C 600
VPmin Positive trigger threshold voltage VDD = 5 TA = –55°C 2.2 V
TA = –40°C 2.2
TA = 25°C 2.2 2.9
TA = 85°C 2.2
TA = 125°C 2.2
VDD = 10 TA = –55°C 4.6
TA = –40°C 4.6
TA = 25°C 4.6 5.9
TA = 85°C 4.6
TA = 125°C 4.6
VDD = 15 TA = –55°C 6.8
TA = –40°C 6.8
TA = 25°C 6.8 8.8
TA = 85°C 6.8
TA = 125°C 6.8
VPmax Positive trigger threshold voltage VDD = 5 TA = –55°C 3.6 V
TA = –40°C 3.6
TA = 25°C 2.9 3.6
TA = 85°C 3.6
TA = 125°C 3.6
VDD = 10 TA = –55°C 7.1
TA = –40°C 7.1
TA = 25°C 5.9 7.1
TA = 85°C 7.1
TA = 125°C 7.1
VDD = 15 TA = –55°C 10.8
TA = –40°C 10.8
TA = 25°C 8.8 10.8
TA = 85°C 10.8
TA = 125°C 10.8
VNmin Negative trigger threshold voltage VDD = 5 TA = –55°C 0.9 V
TA = –40°C 0.9
TA = 25°C 0.9 1.9
TA = 85°C 0.9
TA = 125°C 0.9
VDD = 10 TA = –55°C 2.5
TA = –40°C 2.5
TA = 25°C 2.5 3.9
TA = 85°C 2.5
TA = 125°C 2.5
VDD = 15 TA = –55°C 4
TA = –40°C 4
TA = 25°C 4 5.8
TA = 85°C 4
TA = 125°C 4
VNmax Negative trigger threshold voltage VDD = 5 TA = –55°C 2.8 V
TA = –40°C 2.8
TA = 25°C 1.9 2.8
TA = 85°C 2.8
TA = 125°C 2.8
VDD = 10 TA = –55°C 5.2
TA = –40°C 5.2
TA = 25°C 3.9 5.2
TA = 85°C 5.2
TA = 125°C 5.2
VDD = 15 TA = –55°C 7.4
TA = –40°C 7.4
TA = 25°C 5.8 7.4
TA = 85°C 7.4
TA = 125°C 7.4
VHmin Hysteresis voltage VDD = 5 TA = –55°C 0.3 V
TA = –40°C 0.3
TA = 25°C 0.3 0.9
TA = 85°C 0.3
TA = 125°C 0.3
VDD = 10 TA = –55°C 1.2
TA = –40°C 1.2
TA = 25°C 1.2 2.3
TA = 85°C 1.2
TA = 125°C 1.2
VDD = 15 TA = –55°C 1.6
TA = –40°C 1.6
TA = 25°C 1.6 3.5
TA = 85°C 1.6
TA = 125°C 1.6
VHmax Hysteresis voltage VDD = 5 TA = –55°C 1.6 V
TA = –40°C 1.6
TA = 25°C 0.9 1.6
TA = 85°C 1.6
TA = 125°C 1.6
VDD = 10 TA = –55°C 3.4
TA = –40°C 3.4
TA = 25°C 2.3 3.4
TA = 85°C 3.4
TA = 125°C 3.4
VDD = 15 TA = –55°C 5
TA = –40°C 5
TA = 25°C 3.5 5
TA = 85°C 5
TA = 125°C 5
IOLmin Output low (sink) current VO = 0.4, VIN = 0 or 5,
VDD = 5		 TA = –55°C 0.64 mA
TA = –40°C 0.61
TA = 25°C 0.51 1
TA = 85°C 0.42
TA = 125°C 0.36
VO = 0.5, VIN = 0 or 10,
VDD = 10		 TA = –55°C 1.6
TA = –40°C 1.5
TA = 25°C 1.3 2.6
TA = 85°C 1.1
TA = 125°C 0.9
VO = 1.5, VIN = 0 or 15,
VDD = 15		 TA = –55°C 4.2
TA = –40°C 4
TA = 25°C 3.4 6.8
TA = 85°C 2.8
TA = 125°C 2.4
IOHmin Output high (source) current VO = 4.6, VIN = 0 or 5,
VDD = 5		 TA = –55°C –0.64 mA
TA = –40°C –0.61
TA = 25°C –0.51 –1
TA = 85°C –0.42
TA = 125°C –0.36
VO = 2.5, VIN = 0 or 5,
VDD = 5		 TA = –55°C –2
TA = –40°C –1.8
TA = 25°C –1.6 –3.2
TA = 85°C –1.3
TA = 125°C –1.15
VO = 9.5, VIN = 0 or 10,
VDD = 10		 TA = –55°C –1.6
TA = –40°C –1.5
TA = 25°C –1.3 –2.6
TA = 85°C –1.1
TA = 125°C –0.9
VO = 13.5, VIN = 0 or 15,
VDD = 15		 TA = –55°C –4.2
TA = –40°C –4
TA = 25°C –3.4 –6.8
TA = 85°C –2.8
TA = 125°C –2.4
VOLmax Low-level output voltage VIN = 5, VDD = 5 TA = –55°C, –40°C,
25°C, 85°C, and 125°C		 0 0.05 V
VIN = 10, VDD = 10 TA = –55°C, –40°C,
25°C, 85°C, and 125°C		 0 0.05
VIN = 15, VDD = 15 TA = –55°C, –40°C,
25°C, 85°C, and 125°C		 0 0.05
VOHmin High-level output voltage VIN = 0, VDD = 5 TA = –55°C, –40°C,
25°C, 85°C, and 125°C		 4.95 5 V
VIN = 0, VDD = 10 TA = –55°C, –40°C,
25°C, 85°C, and 125°C		 9.95 10
VIN = 0, VDD = 15 TA = –55°C, –40°C,
25°C, 85°C, and 125°C		 14.95 15
IINmax Input current VIN = 0 or 18, VDD = 18 TA = –55°C ±0.1 µA
TA = –40°C ±0.1
TA = 25°C ±0.00001 ±0.1
TA = 85°C ±1
TA = 125°C ±1

6.6 Electrical Characteristics: Dynamic

at TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, and RL = 200 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHL,
tPLH 		Propagation delay time VDD = 5 140 280 ns
VDD = 10 70 140
VDD = 15 60 120
tTHL,
tTLH		 Transition time VDD = 5 100 200 ns
VDD = 10 50 100
VDD = 15 40 80
CIN Input capacitance Any input 5 7.5 pF

6.7 Typical Characteristics

CD40106B D001_SCHS063.gif Figure 1. Typical Output Low (Sink)
Current Characteristics
CD40106B D003_SCHS063.gif Figure 3. Typical Output High (Source)
Current Characteristics
CD40106B D016_Des_SCHS097.gif Figure 5. Typical Current and Voltage
Transfer Characteristics
CD40106B D018_SCHS097.gif Figure 7. Typical Propagation Delay Time as a
Function of Load Capacitance
CD40106B D019_SCHS097.gif Figure 9. Typical Power Dissipation Per Trigger as a
Function of Input Frequency
CD40106B D021_SCHS097.gif Figure 11. Typical Percent Hysteresis as a Function of Supply Voltage
CD40106B D002_SCHS063.gif Figure 2. Minimum Output Low (Sink)
Current Characteristics
CD40106B D004_SCHS063.gif Figure 4. Minimum Output High (Source)
Current Characteristics
CD40106B D017_Des_SCHS097.gif Figure 6. Typical Voltage Transfer Characteristics as a
Function of Temperature
CD40106B D010_SCHS063.gif Figure 8. Typical Transition Time as a
Function of Load Capacitance
CD40106B D020_SCHS097.gif Figure 10. Typical Trigger Threshold Voltage as a
Function of Supply Voltage

7 Parameter Measurement Information

CD40106B Input_Output_Char_SCHS097.gif Figure 12. Input and Output Characteristics
CD40106B Hyst_Def_Char_Test_SetUp_SCHS097.gif Figure 13. Hysteresis Definition, Characteristics, and Test Set-Up
CD40106B Quies_Dev_Curr_Test_Circ_SCHS063.gif Figure 14. Quiescent Device Current Test Circuit
CD40106B Input_Curr_Test_Circ_SCHS063.gif Figure 15. Input Current Test Circuit
CD40106B Dyn_Pwr_Diss_Test_Circ_SCHS097.gif Figure 16. Dynamic Power Dissipation Test Circuit

 
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