SCHS032D November 1998 – July 2021 CD4027B
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
CHARACTERISTIC | VDD (V) |
LIMITS | UNIT | |||
---|---|---|---|---|---|---|
ALL PACKAGES | ||||||
MIN | TYP | MAX | ||||
Propagation Delay Time | 5 | 150 | 300 | ns | ||
Clock to Q or Q Outputs | 10 | 65 | 130 | |||
tPHL, tPLH | 15 | 45 | 90 | |||
Set to Q or Reset to Q, tPLH | 5 | 150 | 300 | ns | ||
10 | 65 | 130 | ||||
15 | 45 | 90 | ||||
Set to Q or Reset to Q, tPHL | 5 | 200 | 400 | ns | ||
10 | 85 | 170 | ||||
15 | 60 | 120 | ||||
Transition Time tTHL, tTLH |
5 | 100 | 200 | ns | ||
10 | 50 | 100 | ||||
15 | 40 | 80 | ||||
Maximum Clock Input | 5 | 3.5 | 7 | MHz | ||
Frequency (Toggle Mode)(1) | 10 | 8 | 16 | |||
fCL | 15 | 12 | 24 | |||
Minimum Clock Pulse Width, tW | 5 | 70 | 140 | |||
10 | 30 | 60 | ||||
15 | 20 | 40 | ||||
Minimum Set or Reset Pulse Width, tW | 5 | 90 | 180 | ns | ||
10 | 40 | 80 | ||||
15 | 25 | 50 | ||||
Minimum Data Setup Time, tS | 5 | 100 | 200 | ns | ||
10 | 35 | 75 | ||||
15 | 25 | 50 | ||||
Clock Input Rise or Fall
Time trCL, tfCL |
5 | 45 | μs | |||
10 | 5 | |||||
15 | 2 | |||||
Input Capacitance, CI | 5 | 7.5 | pF |