SCHS051I November   1998  – May 2024 CD4066B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

CD4066B Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification Figure 6-1 Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
CD4066B Channel On-State Resistance Measurement Circuit Figure 6-2 Channel On-State Resistance Measurement Circuit
CD4066B Typical On Characteristics for One of Four Channels Figure 6-3 Typical On Characteristics for One of Four Channels
CD4066B Off-Switch Input or Output Leakage Figure 6-4 Off-Switch Input or Output Leakage
CD4066B Propagation Delay Time Signal Input (Vis) to Signal Output (Vos) Figure 6-5 Propagation Delay Time Signal Input (Vis) to Signal Output (Vos)
CD4066B Crosstalk-Control Input to Signal Output Figure 6-6 Crosstalk-Control Input to Signal Output
CD4066B Propagation Delay, tPLH, tPHL Control-Signal Output
All unused pins are connected to VSS.
Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).
Figure 6-7 Propagation Delay, tPLH, tPHL Control-Signal Output
CD4066B Maximum Allowable Control-Input Repetition Rate
All unused pins are connected to VSS.
Figure 6-8 Maximum Allowable Control-Input Repetition Rate
CD4066B Input Leakage-Current Test Circuit Figure 6-9 Input Leakage-Current Test Circuit
CD4066B Four-Channel PAM Multiplex System Diagram Figure 6-10 Four-Channel PAM Multiplex System Diagram