Refer to the PDF data sheet for device specific package drawings
The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) | BODY SIZE(3) |
---|---|---|---|
CDx4AC74 | J (CDIP, 14) | 19.56mm × 7.9mm | 19.56mm × 6.67mm |
N (PDIP, 14) | 19.3mm x 9.4mm | 19.3mm x 6.35mm | |
D (SOIC, 14) | 8.65mm x 6mm | 8.65mm x 3.9mm |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
1 CLR | 1 | Input | Channel 1, Clear Input, Active Low |
1D | 2 | Input | Channel 1, Data Input |
1CLK | 3 | Input | Channel 1, Positive edge triggered clock input |
1 PRE | 4 | Input | Channel 1, Preset Input, Active Low |
1Q | 5 | Output | Channel 1, Output |
1 Q | 6 | Output | Channel 1, Inverted Output |
GND | 7 | — | Ground |
2 Q | 8 | Output | Channel 2, Inverted Output |
2Q | 9 | Output | Channel 2, Output |
2 PRE | 10 | Input | Channel 2, Preset Input, Active Low |
2CLK | 11 | Input | Channel 2, Positive edge triggered clock input |
2D | 12 | Input | Channel 2, Data Input |
2 CLR | 13 | Input | Channel 2, Clear Input, Active Low |
VCC | 14 | — | Positive Supply |