SCHS155E November   1998  – May 2024 CD54HC164 , CD54HCT164 , CD74HC164 , CD74HCT164

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics
    5. 4.5 Prerequisite for Switching Characteristics
    6. 4.6 Switching Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Power Supply Recommendations
  9. 8 Layout
    1. 8.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The ’HC164 and ’HCT164 are 8-bit, serial-in, parallel-out, shift registers with asynchronous reset. Data is shifted on the positive edge of Clock (CLK). A LOW on the RESET (CLR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (A and B) are provided, either one can be used as a data enable control.

Device Information
PART NUMBERPACKAGE(1)BODY SIZE (NOM)
CD74HC164MSOIC (14)8.65mm × 3.90mm
CD74HCT164MSOIC (14)8.65mm × 3.90mm
CD74HC164EPDIP (14)19.31mm × 6.35mm
CD74HCT164EPDIP (14)19.31mm × 6.35mm
CD54HC164FCDIP (14)19.55mm × 6.71mm
(1) For all available packages, see Section 11.
CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 Functional Block Diagram Functional Block Diagram