SCHS169D November   1998  – March 2022 CD54HC251 , CD54HCT251 , CD74HC251 , CD74HCT251

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The ’HC251 and ’HCT251 are 8-channel digital multiplexers with three-state outputs, fabricated with high-speed silicongate CMOS technology. Together with the low power consumption of standard CMOS integrated circuits, they possess the ability to drive 10 LSTTL loads. The three-state feature makes them ideally suited for interfacing with bus lines in a bus-oriented system.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD54HC251F CDIP (16) 24.38 mm × 6.92 mm
CD54HCT251F CDIP (16) 24.38 mm × 6.92 mm
CD74HC251M SOIC (16) 9.90 mm × 3.90 mm
CD74HCT251M SOIC (16) 9.90 mm × 3.90 mm
CD74HC251E PDIP (16) 19.31 mm × 6.35 mm
CD74HCT251E PDIP (16) 19.31 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20220304-SS0I-KJR6-ZKL7-D1SJDL2HKDQG-low.gif Functional Block Diagram