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CDx4HC86 Quadruple 2-Input XOR Gates
- SCHS137E August 1997 – June 2021 CD54HC86 , CD74HC86
  
  PRODUCTION DATA

CONTENTS
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CDx4HC86 Quadruple 2-Input XOR Gates

1 Features
2 Applications
3 Description
4 Revision History
5 Pin Configuration and Functions
1. Pin Functions
6 Specifications
7 Parameter Measurement Information
8 Detailed Description
9 Application and Implementation
1. 9.1 Application Information
2. 9.2 Typical Application
10Power Supply Recommendations
11Layout
1. 11.1 Layout Guidelines
2. 11.2 Layout Example
12Device and Documentation Support
13Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

J|14

Thermal pad, mechanical data (Package|Pins)

Orderable Information

schs137e_oa
schs137e_pm

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DATA SHEET

CDx4HC86 Quadruple 2-Input XOR Gates

1 Features

Buffered inputs
Wide operating voltage range: 2 V to 6 V
Wide operating temperature range: -55°C to +125°C
Supports fanout up to 10 LSTTL loads
Significant power reduction compared to LSTTL logic ICs

2 Applications

Detect phase differences in input signals
Create a selectable inverter / buffer

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