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DATA SHEET
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger
1 Features
- Hysteresis on clock inputs for improved noise
immunity and increased input rise and fall times
- Asynchronous set and reset
- Complementary outputs
- Buffered inputs
- Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF,
TA = 25℃
- Fanout (over temperature range)
- Standard outputs: 10 LSTTL loads
- Bus driver outputs: 15 LSTTL loads
- Wide operating temperature range: -55℃ to 125℃
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL Logic ICs
- HC types
- 2 V to 6 V operation
- High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
- HCT types
- 4.5 V to 5.5 V operation
- Direct LSTTL input logic compatibility, VIL = 0.8 V (max),
VIH = 2 V (min)
- CMOS input compatibility, II ≤ 1 μA at VOL,
VOH
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