SCHS185E September   1997  – April 2022 CD54HCT390 , CD74HC390 , CD74HCT390

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

GUID-20654E66-970D-45DC-A270-8C43E6874C69-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for Push-Pull Outputs
GUID-20201229-CA0I-BXWT-Q7X9-JDBSDCQHTBQJ-low.gifFigure 6-2 Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse Duration
GUID-20201229-CA0I-PGLG-HN2B-WVRKFTLXGRL1-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4 Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays
GUID-20201229-CA0I-XKVX-WCDW-19X6NBQ8QMNT-low.gifFigure 6-3 Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold Times