SCHS202D November   1997  – March 2022 CD54HC4024 , CD54HCT4024 , CD74HC4024 , CD74HCT4024

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Specifications
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD74HC4024M SOIC (14) 8.65 mm × 3.90 mm
CD74HCT4024M SOIC (14) 8.65 mm × 3.90 mm
CD74HC4024E PDIP (14) 19.31 mm × 6.35 mm
CD74HCT4024E PDIP (14) 19.31 mm × 6.35 mm
CD74HC4024PW TSSOP (14) 5.00 mm × 4.40 mm
CD54HC4024F CDIP (14) 19.55 mm × 6.71 mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.
GUID-20220302-SS0I-CP5S-4B16-NCZGK6VVVXQZ-low.gifFunctional Block Diagram