SCHS245D November   1998  – April 2024 CD54AC245 , CD54ACT245 , CD74AC245 , CD74ACT245

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics
    5. 4.5 Switching Characteristics
    6. 4.6 Timing Diagrams
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Links
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|20
  • DW|20
Thermal pad, mechanical data (Package|Pins)

2 Description

The 'AC245 and 'ACT245 are octal-bus transceivers that utilize Advanced CMOS Logic technology.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
CD74AC245/ CD74ACT245 N (PDIP, 20) 24.33mm × 9.4mm 24.33mm × 6.35mm
DW (SOIC, 20) 12.80mm × 10.3mm 12.80mm × 7.50mm
CD54AC245/ CD54ACT245 J (CDIP, 20) 24.2mm × 7.62mm 24.2mm × 6.92mm
CD74ACT245 DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.3mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
GUID-20230202-SS0I-GDCZ-K5KQ-6HJ6KZFWTS9P-low.pngLogic Diagram (Positive Logic)