SCHS312C January   2001  – August 2024 CD54ACT08 , CD74ACT08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
    7. 4.7 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • N|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Pin Configuration and Functions

CD54ACT08 CD74ACT08 CD54ACT08 J Package, 14-Pin CDIP; CD74ACT08 N or D Packages, 14-Pin PDIP or SOIC (Top View) Figure 3-1 CD54ACT08 J Package, 14-Pin CDIP; CD74ACT08 N or D Packages, 14-Pin PDIP or SOIC (Top View)
Table 3-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
1A 1 Input Channel 1, Input A
1B 2 Input Channel 1, Input B
1Y 3 Output Channel 1, Output Y
2A 4 Input Channel 2, Input A
2B 5 Input Channel 2, Input B
2Y 6 Output Channel 2, Output Y
GND 7 — Ground
3Y 8 Output Channel 3, Output Y
3A 9 Input Channel 3, Input A
3B 10 Input Channel 3, Input B
4Y 11 Output Channel 4, Output Y
4A 12 Input Channel 4, Input A
4B 13 Input Channel 4, Input B
VCC 14 — Positive Supply