SCHS181E November 1997 – February 2022 CD54HC367 , CD54HC368 , CD54HCT367 , CD74HC367 , CD74HC368 , CD74HCT367 , CD74HCT368
PRODUCTION DATA
- 1 Features
- 2 Description
- 3 Revision History
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
Package Options
Refer to the PDF data sheet for device specific package drawings
Mechanical Data (Package|Pins)
- N|16
- D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
2 Description
The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. The ’HC367 and ’HCT367 are non-inverting buffers, whereas the ’HC368 and CD74HCT368 are inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs.
| PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
|---|---|---|
| CD74HC367M | SOIC (16) | 9.90 mm × 3.90 mm |
| CD74HC368M | SOIC (16) | 9.90 mm × 3.90 mm |
| CD74HCT367M | SOIC (16) | 9.90 mm × 3.90 mm |
| CD74HCT368M | SOIC (16) | 9.90 mm × 3.90 mm |
| CD74HC367E | PDIP (16) | 19.31 mm × 6.35 mm |
| CD74HC368E | PDIP (16) | 19.31 mm × 6.35 mm |
| CD74HCT367E | PDIP (16) | 19.31 mm × 6.35 mm |
| CD74HCT368E | PDIP (16) | 19.31 mm × 6.35 mm |
| CD54HC367F3A | CDIP (16) | 24.38 mm × 6.92 mm |
| CD54HC368F3A | CDIP (16) | 24.38 mm × 6.92 mm |
| CD54HCT367F3A | CDIP (16) | 24.38 mm × 6.92 mm |
Functional Block
Diagram