SCLS552B December   2003  – April 2024 CD74HC4051-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Recommended Operating Area as a Function of Supply Voltages
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Operating Characteristics
    7. 5.7 Analog Channel Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Analog Channel Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VEE VCC MIN TYP MAX UNIT
CI Switch input capacitance 5 pF
CCOM Common output capacitance 25 pF
fmax Minimum switch frequency response at −3 dB See Figure 6-1 and Figure 5-4, and (1) and (2) −2.25V 2.25V 145 MHz
−4.5V 4.5V 180

THD

 Sine-wave distortion See Figure 6-2 −2.25V 2.25V 0.035 %
−4.5V 4.5V 0.018

OISO

 Switch OFF signal feed through See Figure 6-4 and Figure 5-5, and (2) and (3) −2.25V 2.25V −73 dB
−4.5V 4.5V −75
(1) Adjust input voltage to obtain 0 dBm at VOS for fIN = 1MHz.
(2) VIS is centered at (VCC − VEE)/2.
(3) Adjust input for 0 dBm.