SCHS211F November   1997  – March 2022 CD54HC4094 , CD74HC4094 , CD74HCT4094

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • DYY|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD54HC4094F3A CDIP (16) 24.38 mm × 6.92 mm
CD74HC4094M SOIC (16) 9.90 mm × 3.90 mm
CD74HC4094E PDIP (16) 19.31 mm × 6.35 mm
CD74HC4094NSR SO (16) 6.20 mm × 5.30 mm
CD74HC4094PW TSSOP (16) 5.00 mm × 4.40 mm
CD74HCT4094M SOIC (16) 9.90 mm × 3.90 mm
CD74HCT4094E PDIP (16) 19.31 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20220311-SS0I-JZ6G-NMW5-9N8DL8JGH6M9-low.gif Functional Block Diagram