SCLS595B November   2004  – August 2024 CD74HC4538-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Description
  4. Pin Configuration and Functions
  5. Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Operating Characteristics
    9. 4.9 Typical Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Typical Application
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOmA VCC TA = 25°C TA = −40°C TO 85°C TA = −40°C TO 125°C UNIT
MIN MAX MIN MAX MIN MAX
VOH VI = VIH or VIL CMOS loads −0.02 2 V 1.9 1.9 1.9 V
4.5 V 4.4 4.4 4.4
6 V 5.9 5.9 5.9
TTL loads − 4 4.5 V 3.98 3.84 3.7
−5.2 6 V 5.48 5.34 5.2
VOL VI = VIH or VIL CMOS loads 0.02 2 V 0.1 0.1 0.1 V
4.5 V 0.1 0.1 0.1
6 V 0.1 0.1 0.1
TTL loads 4 4.5 V 0.26 0.33 0.4
5.2 6 V 0.26 0.33 0.4
II VI = VCC or GND A, B, R 6 V ±1 ±1 ±1 μA
RXCX (1) 6 V ±0.05 ±0.05 ±0.05
ICC VI = VCC or GND Quiescent 0 6 V 8 80 160 μA
Active, Q = high, Pins 2 and 14 at VCC/4 0 6 V 0.6 0.8 1 mA
CIN CL = 50 pF 10 10 10 pF
When testing IIL, the Q output must be high. If Q is low (device not triggered), the pullup P device is ON and the low-resistance path from VDD to the test pin causes a current far exceeding the specification.