SCHS134G February   1998  – October 2022 CD54HC73 , CD74HC73 , CD74HCT73

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Specifications
    5. 5.5 Prerequisite for Switching Specifications
    6. 5.6 Switching Specifications
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • N|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Specifications

Input, tr, tf = 6 ns
PARAMETER TEST CONDITIONS VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL

Propagation delay,

CP to Q

 CL = 50 pF 2 160 200 240 ns
4.5 32 40 48
CL = 15 pF 5 13
CL = 50 pF 6 28 34 41
tPLH, tPHL

Propagation delay,

CP to Q

 CL = 50 pF 2 160 200 240 ns
4.5 32 40 48
CL = 15 pF 5 13
CL = 50 pF 6 28 34 41
tPLH, tPHL

Propagation delay,

R to Q, Q

 CL = 50 pF 2 145 180 220 ns
4.5 29 36 44
CL = 15 pF 5 12
CL = 50 pF 6 25 31 38
tTLH, tTHL Output transition time CL = 50 pF 2 75 95 18 110 ns
4.5 15 19 22
6 13 16 19
CI Input capacitance 10 10 10 pF
CPD Power dissipation capacitance(1)(2) 5 28 pF
HCT TYPES
tPLH, tPHL

Propagation delay,

CP to Q

 CL = 50 pF 4.5 38 48 57 ns
tPLH, tPHL

Propagation delay,

CP to Q

 CL = 50 pF 4.5 36 45 54 ns
tPLH, tPHL

Propagation delay,

R to Q, Q

 CL = 50 pF 4.5 34 43 51 ns
tTLH, tTHL Output transition time CL = 50 pF 4.5 15 19 22 ns
CI Input capacitance 10 10 10 pF
CPD Power dissipation capacitance(1)(2) 5 28 pF
(1) CPD is used to determine the dynamic power consumption, per flip-flop.
(2) PD = CPD VCC2fi + ∑ CL VCC2fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.