SCHS158F November   1998  – March 2022 CD54HC173 , CD54HCT173 , CD74HC173 , CD74HCT173

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Prerequisite For Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Switching Characteristics

Input tt = 6ns. Unless otherwise specified, CL = 50pF
PARAMETER VCC(V) 25°C -40°C to 85°C -55°C to 125°C UNIT
TYP MAX MAX MAX
HC TYPES
tpd Propagation delay, clock to output 2 200 250 300 ns
4.5 17(1) 40 50 60
6 34 43 51
tpd Propagation delay, MR to output 2 175 220 265 ns
4.5 12(1) 35 44 53
6 30 37 45
tpd Propagation delay output enable to Q (Figure 6) 2 150 190 225 ns
4.5 12(1) 30 38 45
6 26 33 38
tt Output transition times 2 60 75 90 ns
4.5 12 15 18
6 10 13 15
fMAX Maximum clock frequency 5 60(1) MHz
Ci Input capacitance 10 10 10 pF
CO Three-state output capacitance 10 10 10 pF
Cpd(2)(3) Power dissipation capacitance 5 29 pF
HCT TYPES
tpd Propagation delay, clock to output 4.5 17(1) 40 50 60 ns
tpd Propagation delay, MR to output 4.5 18(1) 44 55 66 ns
tpd Propagation delay output enable to Q (Figure 6) 2 150 190 225 ns
4.5 14(1) 30 38 45
6 26 33 38
tt Output transition times 4.5 15 19 22 ns
fMAX Maximum clock frequency 5 60(1) MHz
Ci Input capacitance 10 10 10 pF
Cpd(2)(3) Power dissipation capacitance 5 34 pF
(1) Typical value tested at 5V, CL = 15pF.
(2) CPD is used to determine th edynamic power consumption, per package.
(3) PD = VCC2fi + Σ (CL VCC2 + fO) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.